From patchwork Tue Oct 7 06:37:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 5043621 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 86E339F295 for ; Tue, 7 Oct 2014 06:40:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A257D2016C for ; Tue, 7 Oct 2014 06:40:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BAEC020166 for ; Tue, 7 Oct 2014 06:40:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XbOPK-0002Ul-3V; Tue, 07 Oct 2014 06:38:02 +0000 Received: from mail-ig0-f201.google.com ([209.85.213.201]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XbOPI-0002Rs-38 for linux-arm-kernel@lists.infradead.org; Tue, 07 Oct 2014 06:38:00 +0000 Received: by mail-ig0-f201.google.com with SMTP id h15so763912igd.4 for ; Mon, 06 Oct 2014 23:37:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=DUTC8MR7ci54+p9mx8zj1icA/C63wJtztVxH65e445c=; b=FMfo/MBdGKQLNhzs9FQSG1KheUej2fh6m/+Y2BVcIsR5F0otvhlsG/6usau3KZnFze WZcb4p8IkDMz1TONI3Ec1Wh6X3TuUluwk6zCs6kVYR2oeUI6p2YnvWKuV427JpVa+3gm 3DsVunLdHBvxB594XxEezEg5l8Zrkq6xXYQ3hVC3spMuZz03Vjc7IBWLjUf6MlW6V8II 3QEkcQchGQYSJNSLRR45EzmbSZnZo7rQnJxd60hSwBPILpuGP9SLmwg/Jjjp1X3jB6SK gXvZ7i6YB68P0l2moUH6NXB8V8P4ZliikPm0S3POZdoW72cZvpNRk693LeYdSiTJLykE Oscw== X-Gm-Message-State: ALoCoQmYuG2g5TSSwnG756d314ofdAdVkn/bvES692qJ+YEC4uoJYenJiMvV+LhU3pGO3giwCIZ7 X-Received: by 10.50.43.168 with SMTP id x8mr14210413igl.4.1412663858013; Mon, 06 Oct 2014 23:37:38 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id j25si824698yhb.0.2014.10.06.23.37.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Oct 2014 23:37:37 -0700 (PDT) Received: from sonnyrao.mtv.corp.google.com ([172.22.162.1]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id 6qRnrObd.1; Mon, 06 Oct 2014 23:37:37 -0700 Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id 1B6CEA0BFB; Mon, 6 Oct 2014 23:37:36 -0700 (PDT) From: Sonny Rao To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] clocksource: arch_timer: Allow the device tree to specify uninitialized CNTVOFF Date: Mon, 6 Oct 2014 23:37:32 -0700 Message-Id: <1412663852-32681-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141006_233800_172634_0E0BA0C2 X-CRM114-Status: GOOD ( 18.21 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Lorenzo Pieralisi , pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, Marc Zyngier , Catalin Marinas , Daniel Lezcano , Will Deacon , linux-kernel@vger.kernel.org, robh+dt@kernel.org, Doug Anderson , galak@codeaurora.org, Sudeep Holla , Olof Johansson , Nathan Lynch , Thomas Gleixner , Sonny Rao , Stephen Boyd X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Doug Anderson Some 32-bit (ARMv7) systems are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset (CNTVOFF) between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) On systems like the above, it doesn't make sense to use the virtual counter. There's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. This adds an optional property which can inform the kernel of this situation, and firmware is free to remove the property if it is going to initialize the CNTVOFF registers when each CPU comes out of reset. Currently, the best course of action in this case is to use the physical timer, which is why it is important that CNTHCTL hasn't been changed from its reset value and it's a reasonable assumption given that the firmware has never entered HYP mode. Note that it's been said that ARM64 (ARMv8) systems the firmware and kernel really can't be architected as described above. That means using the physical timer like this really only makes sense for ARMv7 systems. Signed-off-by: Doug Anderson Signed-off-by: Sonny Rao Reviewed-by: Mark Rutland --- Changes in v2: - Add "#ifdef CONFIG_ARM" as per Will Deacon Changes in v3: - change property name to arm,cntvoff-not-fw-configured and specify that the value of CNTHCTL.PL1PC(T)EN must still be the reset value of 1 as per Mark Rutland --- Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++ drivers/clocksource/arm_arch_timer.c | 9 +++++++++ 2 files changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 37b2caf..67837c9 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -22,6 +22,14 @@ to deliver its interrupts via SPIs. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. +** Optional properties: + +- arm,cntvoff-not-fw-configured : Firmware does not initialize + CNTVOFF, which may reset to arbitrary and different values on each + CPU. CNTHCTL.PL1PC(T)EN must both be 1, which is the reset value + specificed by the architecture. Only supported for ARM (not ARM64). + + Example: timer { diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index bd8da15..234d7b9 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -668,6 +668,15 @@ static void __init arch_timer_init(struct device_node *np) arch_timer_ppi[i] = irq_of_parse_and_map(np, i); arch_timer_detect_rate(NULL, np); +#ifdef CONFIG_ARM + /* + * If we cannot rely on firmware initializing the CNTVOFF then + * we should use the physical timers instead. + */ + if (of_property_read_bool(np, "arm,cntvoff-not-fw-configured")) + arch_timer_use_virtual = false; +#endif + /* * If HYP mode is available, we know that the physical timer * has been configured to be accessible from PL1. Use it, so