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Thu, 16 Oct 2014 10:12:12 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id oh5sm15936141pbc.76.2014.10.16.10.12.11 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 16 Oct 2014 10:12:11 -0700 (PDT) From: Soren Brinkmann To: Linus Walleij Subject: [PATCH RFC v2 5/8] pinctrl: zynq: Support low power mode property Date: Thu, 16 Oct 2014 10:11:32 -0700 Message-Id: <1413479495-14206-6-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 2.1.2.1.g5e69ed6 In-Reply-To: <1413479495-14206-1-git-send-email-soren.brinkmann@xilinx.com> References: <1413479495-14206-1-git-send-email-soren.brinkmann@xilinx.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141016_101233_673425_21E46E62 X-CRM114-Status: GOOD ( 12.58 ) X-Spam-Score: -0.7 (/) Cc: linux-arm-kernel@lists.infradead.org, Steffen Trumtrar , Michal Simek , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , linux-kernel@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - for HSTL type pins, allow setting the low power mode property Signed-off-by: Soren Brinkmann --- drivers/pinctrl/pinctrl-zynq.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index f3fce76c8390..0136bddbb4be 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -879,9 +879,10 @@ static const struct pinmux_ops zynq_pinmux_ops = { }; /* pinconfig */ -#define ZYNQ_PINCONF_TRISTATE BIT(0) -#define ZYNQ_PINCONF_SPEED BIT(8) -#define ZYNQ_PINCONF_PULLUP BIT(12) +#define ZYNQ_PINCONF_TRISTATE BIT(0) +#define ZYNQ_PINCONF_SPEED BIT(8) +#define ZYNQ_PINCONF_PULLUP BIT(12) +#define ZYNQ_PINCONF_DISABLE_RECVR BIT(13) #define ZYNQ_PINCONF_IOTYPE_SHIFT 9 #define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT) @@ -895,6 +896,11 @@ enum zynq_io_standards { zynq_iostd_max }; +static unsigned int zynq_pinconf_iostd_get(u32 reg) +{ + return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT; +} + static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) @@ -930,9 +936,19 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_SLEW_RATE: arg = !!(reg & ZYNQ_PINCONF_SPEED); break; + case PIN_CONFIG_LOW_POWER_MODE: + { + enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg); + + if (iostd != zynq_iostd_hstl) + return -EINVAL; + if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR)) + return -EINVAL; + arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR); + break; + } case PIN_CONFIG_IOSTANDARD: - arg = reg & ZYNQ_PINCONF_IOTYPE_MASK; - arg >>= ZYNQ_PINCONF_IOTYPE_SHIFT; + arg = zynq_pinconf_iostd_get(reg); break; default: return -ENOTSUPP; @@ -994,6 +1010,13 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, } reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT; break; + case PIN_CONFIG_LOW_POWER_MODE: + if (arg) + reg |= ZYNQ_PINCONF_DISABLE_RECVR; + else + reg &= ~ZYNQ_PINCONF_DISABLE_RECVR; + + break; default: dev_warn(pctldev->dev, "unsupported configuration parameter '%u'\n",