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Tue, 21 Oct 2014 14:44:44 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/7] clk: samsung: exynos7: add clocks for I2C block Date: Tue, 21 Oct 2014 11:13:51 +0530 Message-id: <1413870237-1821-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1413870237-1821-1-git-send-email-a.kesavan@samsung.com> References: <1413870237-1821-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRmVeSWpSXmKPExsWyRsSkWvfMJ9cQg48HzC3eL+thtJh/5Byr xabH11gtZpzfx2SxaNt/Zov/e3awW6za9YfRgd1jzbw1jB47Z91l99i0qpPNY/OSeo/Pm+QC WKO4bFJSczLLUov07RK4Mi5decdeMFuqYudtrQbGKWJdjJwcEgImEscPLGGCsMUkLtxbz9bF yMUhJLCUUeLYxo2sMEWrtpxkhUhMZ5RYu+s/O0hCSKCPSeL+TRcQm01AT2LBv6/MILaIgIbE lK7H7CANzALbGCW+rTrPBpIQFnCXOHXxKFgzi4CqxPXrr8BW8wq4SEy8cRuohgNom4LEnEk2 ICangKvEs/0VEKtcJL4svgp2nITAPHaJY6/us0CMEZD4NvkQC0SrrMSmA8wQN0tKHFxxg2UC o/ACRoZVjKKpBckFxUnpRaZ6xYm5xaV56XrJ+bmbGIEBfvrfs4k7GO8fsD7EKMDBqMTDG7HE NUSINbGsuDL3EKMp0IaJzFKiyfnAOMoriTc0NjOyMDUxNTYytzRTEufVkf4ZLCSQnliSmp2a WpBaFF9UmpNafIiRiYNTqoHR41TxrzvPYtL12ldFMvSp7qsVOsMo0vjOc3/6Xs24tfMilMpO y/h3p7xSKO0Iq/3MtOTepltLpjvw+XS8XdLJV2Km/2RG6YYfM0K77iXZB24J4bLgLjcqPVVr 8qOydI/9P+tF7TynM1bW5Z/es0i0dMfD69XftyuXPe55yLj90Iu1HsZfltcqsRRnJBpqMRcV JwIAkr+ffGsCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRmVeSWpSXmKPExsVy+t9jQd0zn1xDDI606Fm8X9bDaDH/yDlW i02Pr7FazDi/j8li0bb/zBb/9+xgt1i16w+jA7vHmnlrGD12zrrL7rFpVSebx+Yl9R6fN8kF sEY1MNpkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAJ2h pFCWmFMKFApILC5W0rfDNCE0xE3XAqYxQtc3JAiux8gADSSsYcy4dOUde8FsqYqdt7UaGKeI dTFyckgImEis2nKSFcIWk7hwbz1bFyMXh5DAdEaJtbv+s4MkhAT6mCTu33QBsdkE9CQW/PvK DGKLCGhITOl6zA7SwCywjVHi26rzbCAJYQF3iVMXj4I1swioSly//ooJxOYVcJGYeOM2UA0H 0DYFiTmTbEBMTgFXiWf7KyBWuUh8WXyVbQIj7wJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5 uZsYwfHzTGoH48oGi0OMAhyMSjy8EUtcQ4RYE8uKK3MPMUpwMCuJ8P6NAQrxpiRWVqUW5ccX leakFh9iNAW6aSKzlGhyPjC280riDY1NzE2NTS1NLEzMLJXEeQ+0WgcKCaQnlqRmp6YWpBbB 9DFxcEo1MKYX/bzg6GvTc+LiQob9YZcOarUEHs+vmXdEul30epDlXEuTax5VV7yDZlX+mnj8 jX3O9MyyyzqNWnEzVJ5sPXVo3rNWV9NMnh2mXdP3BiUf9/vTv+3zym+Tm5/ZsCQq7Bd/sD52 D4uvNqu3KMPDb2Xu1QfKdkZr7fkw+a7AtUzdNfMd3mromymxFGckGmoxFxUnAgCWvRLttQIA AA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141020_224508_942030_D3E62DF7 X-CRM114-Status: GOOD ( 10.32 ) X-Spam-Score: -6.4 (------) Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, robh@kernel.org, catalin.marinas@arm.com, tomasz.figa@gmail.com, Naveen Krishna Ch X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Naveen Krishna Ch Exynos7 supports 12 I2C channels, add the I2C gate clocks to support them. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-exynos7.c | 24 ++++++++++++++++++++++++ include/dt-bindings/clock/exynos7-clk.h | 16 ++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 54206d4..c700f65 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[] __initdata = { }; static struct samsung_gate_clock peric0_gate_clks[] __initdata = { + GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 8, 0, 0), + GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 9, 0, 0), + GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 10, 0, 0), + GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 11, 0, 0), + GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 12, 0, 0), + GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 13, 0, 0), + GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 14, 0, 0), GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", ENABLE_PCLK_PERIC0, 16, 0, 0), @@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = { }; static struct samsung_gate_clock peric1_gate_clks[] __initdata = { + GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 4, 0, 0), + GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 5, 0, 0), + GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 6, 0, 0), + GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 7, 0, 0), + GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 8, 0, 0), GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", ENABLE_PCLK_PERIC1, 9, 0, 0), GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 00fd6de..6d07b6f 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -30,7 +30,14 @@ /* PERIC0 */ #define PCLK_UART0 1 #define SCLK_UART0 2 -#define PERIC0_NR_CLK 3 +#define PCLK_HSI2C0 3 +#define PCLK_HSI2C1 4 +#define PCLK_HSI2C4 5 +#define PCLK_HSI2C5 6 +#define PCLK_HSI2C9 7 +#define PCLK_HSI2C10 8 +#define PCLK_HSI2C11 9 +#define PERIC0_NR_CLK 10 /* PERIC1 */ #define PCLK_UART1 1 @@ -39,7 +46,12 @@ #define SCLK_UART1 4 #define SCLK_UART2 5 #define SCLK_UART3 6 -#define PERIC1_NR_CLK 7 +#define PCLK_HSI2C2 7 +#define PCLK_HSI2C3 8 +#define PCLK_HSI2C6 9 +#define PCLK_HSI2C7 10 +#define PCLK_HSI2C8 11 +#define PERIC1_NR_CLK 12 /* PERIS */ #define PCLK_CHIPID 1