From patchwork Wed Oct 22 13:43:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 5132501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 492A9C11AC for ; Wed, 22 Oct 2014 13:48:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7F3C72013A for ; Wed, 22 Oct 2014 13:48:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A0F582012F for ; Wed, 22 Oct 2014 13:48:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgwFD-0002BO-6E; Wed, 22 Oct 2014 13:46:31 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgwEf-0001vB-Fp for linux-arm-kernel@lists.infradead.org; Wed, 22 Oct 2014 13:45:58 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 168024FF8; Wed, 22 Oct 2014 15:45:40 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from arch.hh.imgtec.org (unknown [190.2.108.156]) by mail.free-electrons.com (Postfix) with ESMTPSA id 385164FC3; Wed, 22 Oct 2014 15:45:35 +0200 (CEST) From: Ezequiel Garcia To: Jason Cooper , Thomas Gleixner Subject: [PATCH 4/7] irqchip: armada-370-xp: Enable Performance Counter interrupts Date: Wed, 22 Oct 2014 10:43:44 -0300 Message-Id: <1413985427-20918-5-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1413985427-20918-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1413985427-20918-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141022_064557_716602_F850ED67 X-CRM114-Status: GOOD ( 11.19 ) X-Spam-Score: -0.5 (/) Cc: Thomas Petazzoni , Andrew Lunn , Tawfik Bayouk , Nadav Haklai , Lior Amsalem , Ezequiel Garcia , Gregory Clement , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In order to get the Performance Counter overflow events (i.e. hardware perf events), we need to unmask the interrupts in the "Coherency Fabric Local Cause" register, which is part of the percpu configuration of the interrupt controller. Signed-off-by: Ezequiel Garcia --- drivers/irqchip/irq-armada-370-xp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 3871c688..387a6a6 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -37,6 +37,8 @@ /* Interrupt Controller Registers Map */ #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) +#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) +#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) #define ARMADA_370_XP_INT_CONTROL (0x00) #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) @@ -54,6 +56,7 @@ #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) +#define ARMADA_370_XP_FABRIC_IRQ (3) #define IPI_DOORBELL_START (0) #define IPI_DOORBELL_END (8) @@ -77,6 +80,7 @@ static inline bool is_percpu_irq(irq_hw_number_t irq) { switch (irq) { case ARMADA_370_XP_TIMER0_PER_CPU_IRQ: + case ARMADA_370_XP_FABRIC_IRQ: return true; default: return false; @@ -297,12 +301,17 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, static void armada_xp_mpic_smp_cpu_init(void) { + unsigned long cpuid = cpu_logical_map(smp_processor_id()); u32 control; int nr_irqs, i; control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); nr_irqs = (control >> 2) & 0x3ff; + /* Enable Performance Counter Overflow interrupts */ + writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), + per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS); + for (i = 0; i < nr_irqs; i++) writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);