From patchwork Wed Oct 22 16:06:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 5135661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5086E9F3ED for ; Wed, 22 Oct 2014 16:25:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 760C020120 for ; Wed, 22 Oct 2014 16:25:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A5A8200E1 for ; Wed, 22 Oct 2014 16:25:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgygT-0001CT-67; Wed, 22 Oct 2014 16:22:49 +0000 Received: from mail-pd0-f173.google.com ([209.85.192.173]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgyR5-00061o-MS for linux-arm-kernel@lists.infradead.org; Wed, 22 Oct 2014 16:06:56 +0000 Received: by mail-pd0-f173.google.com with SMTP id g10so3795939pdj.32 for ; Wed, 22 Oct 2014 09:06:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Gofcc2M+ADUKiXQe5NB7+Q1hjtrPvjDCD9ICXE6tZgc=; b=C1fUrpkCl0alrbl8pcGK1lThDaQyDfAAkt5GyQGXYugeK44QHGPL7yiNaUNBbTs3JI 5qtTa8LRjG3D0qlEYvzNVpIXTTnyp08bwleALObRjP+32YkGKQSkGpCNl63N1cVDvpDq NidsEaGIkgTG4mWbOE95Nkn9z3EZ1XZcQs5FiXGv+z/r+PMouiRO38V5Tl6EXo50ds6p aVAkScLsub+gQFxMsszUwZnRfdGH25VITtCfV1XZrpYF69iw5tFaHu9KZyONEYlxhVvp I1535JTs4VQhMhkORzvSl8Uf57D57FAA/kiYKYozpTudQnWf6MJOf1Q0wNznj5I0wk1D WqfQ== X-Gm-Message-State: ALoCoQlU3tk8eMxONW3N81ObvYYXFt8Qkub7Ifwj93oem6w4y80+Rhoo/OGAA3Ju8QadsfE7dk7n X-Received: by 10.66.121.103 with SMTP id lj7mr43751501pab.84.1413993993349; Wed, 22 Oct 2014 09:06:33 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPSA id y16sm14567644pbt.17.2014.10.22.09.06.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Oct 2014 09:06:32 -0700 (PDT) From: mathieu.poirier@linaro.org To: linux@arm.linux.org.uk Subject: [PATCH] ARM: supplementing IO accessors with 64 bit capability Date: Wed, 22 Oct 2014 10:06:23 -0600 Message-Id: <1413993983-17310-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141022_090655_759018_D0196B02 X-CRM114-Status: UNSURE ( 9.71 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.2 (-) Cc: thomas.petazzoni@free-electrons.com, mathieu.poirier@linaro.org, stefano.stabellini@eu.citrix.com, catalin.marinas@arm.com, Liviu.Dudau@arm.com, linux-kernel@vger.kernel.org, ezequiel.garcia@free-electrons.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mathieu Poirier Some drivers on ARMv7 need 64 bit read and writes. Signed-off-by: Mathieu Poirier --- arch/arm/include/asm/io.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 1805674..861e52c 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -118,6 +118,24 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) return val; } +#if __LINUX_ARM_ARCH__ >= 5 +static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +{ + asm volatile("strd %1, %0" + : "+Qo" (*(volatile u64 __force *)addr) + : "r" (val)); +} + +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + asm volatile("ldrd %1, %0" + : "+Qo" (*(volatile u64 __force *)addr), + "=r" (val)); + return val; +} +#endif + /* * Architecture ioremap implementation. */ @@ -306,10 +324,13 @@ extern void _memset_io(volatile void __iomem *, int, size_t); __raw_readw(c)); __r; }) #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) #define writeb_relaxed(v,c) __raw_writeb(v,c) #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) +#define writeq_relaxed(v,c) __raw_writeq((__force u64) cpu_to_le64(v),c) #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })