| Message ID | 1414002412-13615-7-git-send-email-sebastian.hesselbarth@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 22.10.2014 20:26, Sebastian Hesselbarth wrote: > Marvell BG2 has two fast ethernet controllers with internal PHY, > add the corresponding nodes to SoC dtsi. > > Tested-by: Antoine Ténart <antoine.tenart@free-electrons.com> > Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> > Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Applied the four DT patches to berlin/dt. Sebastian > --- > Changelog: > v1->v2: > - move phy-connection-type to controller node instead of PHY node > (Reported by Sergei Shtylyov) > > Cc: "David S. Miller" <davem@davemloft.net> > Cc: "Antoine Ténart" <antoine.tenart@free-electrons.com> > Cc: Florian Fainelli <f.fainelli@gmail.com> > Cc: Eric Miao <eric.y.miao@gmail.com> > Cc: Haojian Zhuang <haojian.zhuang@gmail.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: netdev@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > --- > arch/arm/boot/dts/berlin2.dtsi | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi > index 9d7c810ebd0b..dc0227dfc691 100644 > --- a/arch/arm/boot/dts/berlin2.dtsi > +++ b/arch/arm/boot/dts/berlin2.dtsi > @@ -79,11 +79,47 @@ > clocks = <&chip CLKID_TWD>; > }; > > + eth1: ethernet@b90000 { > + compatible = "marvell,pxa168-eth"; > + reg = <0xb90000 0x10000>; > + clocks = <&chip CLKID_GETH1>; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; > + /* set by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + #address-cells = <1>; > + #size-cells = <0>; > + phy-connection-type = "mii"; > + phy-handle = <ðphy1>; > + status = "disabled"; > + > + ethphy1: ethernet-phy@0 { > + reg = <0>; > + }; > + }; > + > cpu-ctrl@dd0000 { > compatible = "marvell,berlin-cpu-ctrl"; > reg = <0xdd0000 0x10000>; > }; > > + eth0: ethernet@e50000 { > + compatible = "marvell,pxa168-eth"; > + reg = <0xe50000 0x10000>; > + clocks = <&chip CLKID_GETH0>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + /* set by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + #address-cells = <1>; > + #size-cells = <0>; > + phy-connection-type = "mii"; > + phy-handle = <ðphy0>; > + status = "disabled"; > + > + ethphy0: ethernet-phy@0 { > + reg = <0>; > + }; > + }; > + > apb@e80000 { > compatible = "simple-bus"; > #address-cells = <1>; >
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 9d7c810ebd0b..dc0227dfc691 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -79,11 +79,47 @@ clocks = <&chip CLKID_TWD>; }; + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + cpu-ctrl@dd0000 { compatible = "marvell,berlin-cpu-ctrl"; reg = <0xdd0000 0x10000>; }; + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>;