From patchwork Sat Oct 25 14:48:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 5151381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3550C9F349 for ; Sat, 25 Oct 2014 14:54:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 638A4202E9 for ; Sat, 25 Oct 2014 14:54:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 32437202C8 for ; Sat, 25 Oct 2014 14:54:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xi2gZ-000526-OO; Sat, 25 Oct 2014 14:51:19 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xi2gC-0004wG-BA for linux-arm-kernel@lists.infradead.org; Sat, 25 Oct 2014 14:50:57 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id D495B4735; Sat, 25 Oct 2014 16:50:41 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from arch.hh.imgtec.org (unknown [190.2.108.156]) by mail.free-electrons.com (Postfix) with ESMTPSA id 0598A46E3; Sat, 25 Oct 2014 16:50:37 +0200 (CEST) From: Ezequiel Garcia To: Jason Cooper , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck Subject: [PATCH v2 4/4] ARM: mvebu: Enable the reference clock for timer and watchdog on Armada 375 SoC Date: Sat, 25 Oct 2014 11:48:42 -0300 Message-Id: <1414248522-16055-5-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1414248522-16055-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1414248522-16055-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141025_075056_561127_6CEDEAFD X-CRM114-Status: UNSURE ( 8.81 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.5 (/) Cc: Lior Amsalem , Thomas Petazzoni , linux-watchdog@vger.kernel.org, Tawfik Bayouk , Andrew Lunn , Nadav Haklai , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Now that the timer and watchdog drivers support the Armada 375 usage of the reference clock, we can enable it in the devicetree. Signed-off-by: Ezequiel Garcia Reviewed-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-375.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index de65714..9721e55 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -36,6 +36,12 @@ #clock-cells = <0>; clock-frequency = <2000000000>; }; + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; cpus { @@ -366,13 +372,15 @@ <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <&mpic 5>, <&mpic 6>; - clocks = <&coreclk 0>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; }; watchdog@20300 { compatible = "marvell,armada-375-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; - clocks = <&coreclk 0>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; }; cpurst@20800 {