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Tue, 28 Oct 2014 20:21:07 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, s.nawrocki@samsung.com Subject: [PATCH v3 3/5] clk: samsung: exynos7: add clocks for RTC block Date: Tue, 28 Oct 2014 16:48:53 +0530 Message-id: <1414495135-25588-4-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1414495135-25588-1-git-send-email-a.kesavan@samsung.com> References: <1414495135-25588-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOLMWRmVeSWpSXmKPExsWyRsSkTlelxj/EYMEuFotNj6+xWsw4v4/J YtG2/8wWh9+0s1qs2vWH0YHVY+esu+wem5fUe/RtWcXo8XmTXABLFJdNSmpOZllqkb5dAlfG g8e32QomqFec+arYwPhUoYuRg0NCwESiaYVIFyMnkCkmceHeerYuRi4OIYGljBIrFj5mhUiY SDxsWMYCkVjEKPF2+QFWCKePSWLKtp1MIFVsAnoSC/59ZQaZKiLgIHG6VRAkzCyQJ/H87x12 EFtYwF1i26/FYOUsAqoSO/fuB4vzCrhKbJ3xgRniIAWJOZNsQMKcAm4ST3u+MYPYQkAlnTPf MUHc08wusaopAGKMgMS3yYdYIFplJTYdYIYokZQ4uOIGywRG4QWMDKsYRVMLkguKk9KLDPWK E3OLS/PS9ZLzczcxAsP39L9nvTsYbx+wPsQowMGoxMNr8NAvRIg1say4MvcQoynQhonMUqLJ +cAoySuJNzQ2M7IwNTE1NjK3NFMS51WU+hksJJCeWJKanZpakFoUX1Sak1p8iJGJg1OqgXHb x5VtLw2EV9jf9nt1WkBvwZxDJx+fmMN7KibRy9NGlvnYiZilOlvfnzt20DriWIXUsr5be8rT uzetDfg4Q/JEuOmEau/8N7+r3GUFD22a/WFNbvW3BQ0pSeU90U4sPw0j4n7an931O+Ii53d1 8xuJB87cWj69XupTVvVPkQ8O2vVxe6T+cHEqsRRnJBpqMRcVJwIAcBkFgFoCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprMIsWRmVeSWpSXmKPExsVy+t9jAV3lGv8Qg4MrTC02Pb7GajHj/D4m i0Xb/jNbHH7TzmqxatcfRgdWj52z7rJ7bF5S79G3ZRWjx+dNcgEsUQ2MNhmpiSmpRQqpecn5 KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAe5UUyhJzSoFCAYnFxUr6dpgm hIa46VrANEbo+oYEwfUYGaCBhDWMGQ8e32YrmKBecearYgPjU4UuRk4OCQETiYcNy1ggbDGJ C/fWs3UxcnEICSxilHi7/AArhNPHJDFl204mkCo2AT2JBf++MncxcnCICDhInG4VBAkzC+RJ PP97hx3EFhZwl9j2azFYOYuAqsTOvfvB4rwCrhJbZ3wAa5UQUJCYM8kGJMwp4CbxtOcbM4gt BFTSOfMd0wRG3gWMDKsYRVMLkguKk9JzDfWKE3OLS/PS9ZLzczcxgiPkmdQOxpUNFocYBTgY lXh4DR76hQixJpYVV+YeYpTgYFYS4Y2I8Q8R4k1JrKxKLcqPLyrNSS0+xGgKdNREZinR5Hxg 9OaVxBsam5ibGptamliYmFkqifMeaLUOFBJITyxJzU5NLUgtgulj4uCUamCcvixaaHdIwWsJ swfPn67eU5989cGG9ntxT8ucvn40F0x13hfoXzL9QMEPHqd3YXdyw2vDpqsJ3Nvw/3P/lm69 ohU21pOFpWcqz13+qYbXwlvug8bSmrSIpHUL2W+UdSU6ZiisPVxql7g2cNH+HY9i3jrkS05a fP3bvwmTRZ6sms97vvzftn/8SizFGYmGWsxFxYkA+QQhXqYCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141028_042129_586979_D2EEA580 X-CRM114-Status: GOOD ( 12.75 ) X-Spam-Score: -5.6 (-----) Cc: Naveen Krishna Ch , linux-samsung-soc@vger.kernel.org, tomasz.figa@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Naveen Krishna Ch Add clock support for the RTC block in Exynos7. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan --- .../devicetree/bindings/clock/exynos7-clock.txt | 5 ++ drivers/clk/samsung/clk-exynos7.c | 54 ++++++++++++++++++++ include/dt-bindings/clock/exynos7-clk.h | 7 ++- 3 files changed, 65 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt index b29cb50..6d3d5f8 100644 --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt @@ -28,6 +28,7 @@ Required Properties for Clock Controller: - "samsung,exynos7-clock-topc" - "samsung,exynos7-clock-top0" - "samsung,exynos7-clock-top1" + - "samsung,exynos7-clock-ccore" - "samsung,exynos7-clock-peric0" - "samsung,exynos7-clock-peric1" - "samsung,exynos7-clock-peris" @@ -60,6 +61,10 @@ Input clocks for top1 clock controller: - dout_sclk_cc_pll - dout_sclk_mfc_pll +Input clocks for ccore clock controller: + - fin_pll + - dout_aclk_ccore_133 + Input clocks for peric0 clock controller: - fin_pll - dout_aclk_peric0_66 diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index f5e43fa..3a30f43 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -29,7 +29,9 @@ #define AUD_PLL_CON0 0x0140 #define MUX_SEL_TOPC0 0x0200 #define MUX_SEL_TOPC1 0x0204 +#define MUX_SEL_TOPC2 0x0208 #define MUX_SEL_TOPC3 0x020C +#define DIV_TOPC0 0x0600 #define DIV_TOPC1 0x0604 #define DIV_TOPC3 0x060C @@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = { AUD_PLL_CON0, MUX_SEL_TOPC0, MUX_SEL_TOPC1, + MUX_SEL_TOPC2, MUX_SEL_TOPC3, + DIV_TOPC0, DIV_TOPC1, DIV_TOPC3, }; @@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = { MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, MUX_SEL_TOPC1, 16, 1), + MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), + MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), }; static struct samsung_div_clock topc_div_clks[] __initdata = { + DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", + DIV_TOPC0, 4, 4), + DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", DIV_TOPC1, 24, 4), @@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct device_node *np) CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", exynos7_clk_top1_init); +/* Register Offset definitions for CMU_CCORE (0x105B0000) */ +#define MUX_SEL_CCORE 0x0200 +#define DIV_CCORE 0x0600 +#define ENABLE_ACLK_CCORE0 0x0800 +#define ENABLE_ACLK_CCORE1 0x0804 +#define ENABLE_PCLK_CCORE 0x0900 + +/* + * List of parent clocks for Muxes in CMU_CCORE + */ +PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; + +static unsigned long ccore_clk_regs[] __initdata = { + MUX_SEL_CCORE, + ENABLE_PCLK_CCORE, +}; + +static struct samsung_mux_clock ccore_mux_clks[] __initdata = { + MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, + MUX_SEL_CCORE, 1, 1), +}; + +static struct samsung_gate_clock ccore_gate_clks[] __initdata = { + GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", + ENABLE_PCLK_CCORE, 8, 0, 0), +}; + +static struct samsung_cmu_info ccore_cmu_info __initdata = { + .mux_clks = ccore_mux_clks, + .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), + .gate_clks = ccore_gate_clks, + .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), + .nr_clk_ids = CCORE_NR_CLK, + .clk_regs = ccore_clk_regs, + .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), +}; + +static void __init exynos7_clk_ccore_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &ccore_cmu_info); +} + +CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", + exynos7_clk_ccore_init); + /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ #define MUX_SEL_PERIC0 0x0200 #define ENABLE_PCLK_PERIC0 0x0900 diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index ff63c4e..dd89aa0 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -16,7 +16,8 @@ #define DOUT_SCLK_BUS1_PLL 3 #define DOUT_SCLK_CC_PLL 4 #define DOUT_SCLK_MFC_PLL 5 -#define TOPC_NR_CLK 6 +#define DOUT_ACLK_CCORE_133 6 +#define TOPC_NR_CLK 7 /* TOP0 */ #define DOUT_ACLK_PERIC1 1 @@ -38,6 +39,10 @@ #define CLK_SCLK_MMC0 8 #define TOP1_NR_CLK 9 +/* CCORE */ +#define PCLK_RTC 1 +#define CCORE_NR_CLK 2 + /* PERIC0 */ #define PCLK_UART0 1 #define SCLK_UART0 2