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Tue, 28 Oct 2014 20:21:37 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, s.nawrocki@samsung.com Subject: [PATCH v3 4/5] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks Date: Tue, 28 Oct 2014 16:48:54 +0530 Message-id: <1414495135-25588-5-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1414495135-25588-1-git-send-email-a.kesavan@samsung.com> References: <1414495135-25588-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJLMWRmVeSWpSXmKPExsWyRsSkWtexxj/EYNMOQ4tNj6+xWsw4v4/J YtG2/8wWh9+0s1qs2vWH0YHVY+esu+wem5fUe/RtWcXo8XmTXABLFJdNSmpOZllqkb5dAlfG ziPz2AtmSFW8uLGUvYHxs2gXIyeHhICJxML9NxghbDGJC/fWs3UxcnEICSxllOjftYoZpmju vaNMEIlFjBKzFi+DqupjkrjftAisnU1AT2LBv69AHRwcIgIOEqdbBUHCzAJ5Es//3mEHsYUF YiT+rJnABmKzCKhK/Nv5AMzmFXCVmDlhLyNIq4SAgsScSTYgYU4BN4mnPd/AbhACKumc+Y4J 4p5mdonLs1ghxghIfJt8iAWiVVZi0wGokyUlDq64wTKBUXgBI8MqRtHUguSC4qT0IhO94sTc 4tK8dL3k/NxNjMAQPv3v2YQdjPcOWB9iFOBgVOLhNXjoFyLEmlhWXJl7iNEUaMNEZinR5Hxg pOSVxBsamxlZmJqYGhuZW5opifO+lvoZLCSQnliSmp2aWpBaFF9UmpNafIiRiYNTqoFRzvfg +zo17iMb9531Fi0R/XScb0b90y2LHu+8NqXae5+GwukXDxW7pikcP6/xVNd2V6LXcq7Vj+x+ PA0Si0iYn6+1Oenq/CdHTWP1a96GHGr4n8hzZh3fTA1n3rPbFgnOue2WynKIky1zxc0pEzTE 2HffY7bn+Dz5stk1a4t3slbfNws5TA3/p8RSnJFoqMVcVJwIAOC93zhcAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCIsWRmVeSWpSXmKPExsVy+t9jAV3HGv8Qg1U7FSw2Pb7GajHj/D4m i0Xb/jNbHH7TzmqxatcfRgdWj52z7rJ7bF5S79G3ZRWjx+dNcgEsUQ2MNhmpiSmpRQqpecn5 KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAe5UUyhJzSoFCAYnFxUr6dpgm hIa46VrANEbo+oYEwfUYGaCBhDWMGTuPzGMvmCFV8eLGUvYGxs+iXYycHBICJhJz7x1lgrDF JC7cW8/WxcjFISSwiFFi1uJlUE4fk8T9pkWMIFVsAnoSC/59Ze5i5OAQEXCQON0qCBJmFsiT eP73DjuILSwQI/FnzQQ2EJtFQFXi384HYDavgKvEzAl7GUFaJQQUJOZMsgEJcwq4STzt+cYM YgsBlXTOfMc0gZF3ASPDKkbR1ILkguKk9FwjveLE3OLSvHS95PzcTYzgGHkmvYNxVYPFIUYB DkYlHl7Dh34hQqyJZcWVuYcYJTiYlUR4I2L8Q4R4UxIrq1KL8uOLSnNSiw8xmgIdNZFZSjQ5 Hxi/eSXxhsYm5qbGppYmFiZmlkrivAdbrQOFBNITS1KzU1MLUotg+pg4OKUaGJsurL54bprP W5OWWG7B6UnxWyTOXezQDj3J4bAqv/ddt+nz7Ruqyq3Z9525Wylr1bE4wP3J0YrA0MVHRZT5 //MGRU3IrT9h5+It+MGFM6TZrbaUwcXyUrawgVvbc1eTnCW180psw3xn3tW9GB5+bXHBxnkB LcWySlfeZ0tmZadqhi6rD9mmxFKckWioxVxUnAgAZQip4KcCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141028_042200_493225_01605DA8 X-CRM114-Status: GOOD ( 10.48 ) X-Spam-Score: -5.6 (-----) Cc: Naveen Krishna Ch , linux-samsung-soc@vger.kernel.org, tomasz.figa@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Naveen Krishna Ch Add clock support for the watchdog timer, pwm timer and thermal management unit IPs in Exynos7. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-exynos7.c | 14 ++++++++++++++ include/dt-bindings/clock/exynos7-clk.h | 9 +++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 3a30f43..17e5cf4 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = { ENABLE_PCLK_PERIC0, 14, 0, 0), GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", ENABLE_PCLK_PERIC0, 16, 0, 0), + GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 21, 0, 0), GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", ENABLE_SCLK_PERIC0, 16, 0, 0), + GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), }; static struct samsung_cmu_info peric0_cmu_info __initdata = { @@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", /* Register Offset definitions for CMU_PERIS (0x10040000) */ #define MUX_SEL_PERIS 0x0200 +#define ENABLE_PCLK_PERIS 0x0900 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 +#define ENABLE_SCLK_PERIS 0x0A00 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 /* List of parent clocks for Muxes in CMU_PERIS */ @@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; static unsigned long peris_clk_regs[] __initdata = { MUX_SEL_PERIS, + ENABLE_PCLK_PERIS, ENABLE_PCLK_PERIS_SECURE_CHIPID, + ENABLE_SCLK_PERIS, ENABLE_SCLK_PERIS_SECURE_CHIPID, }; @@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[] __initdata = { }; static struct samsung_gate_clock peris_gate_clks[] __initdata = { + GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", + ENABLE_PCLK_PERIS, 6, 0, 0), + GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", + ENABLE_PCLK_PERIS, 10, 0, 0), + GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), + + GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), }; static struct samsung_cmu_info peris_cmu_info __initdata = { diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index dd89aa0..f255bb7 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -53,7 +53,9 @@ #define PCLK_HSI2C9 7 #define PCLK_HSI2C10 8 #define PCLK_HSI2C11 9 -#define PERIC0_NR_CLK 10 +#define PCLK_PWM 10 +#define SCLK_PWM 11 +#define PERIC0_NR_CLK 12 /* PERIC1 */ #define PCLK_UART1 1 @@ -72,7 +74,10 @@ /* PERIS */ #define PCLK_CHIPID 1 #define SCLK_CHIPID 2 -#define PERIS_NR_CLK 3 +#define PCLK_WDT 3 +#define PCLK_TMU 4 +#define SCLK_TMU 5 +#define PERIS_NR_CLK 6 /* FSYS0 */ #define ACLK_MMC2 1