From patchwork Mon Nov 10 10:43:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minghuan Lian X-Patchwork-Id: 5265341 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9A8C19F3ED for ; Mon, 10 Nov 2014 10:45:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7BB3E2010F for ; Mon, 10 Nov 2014 10:45:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CA4C200DE for ; Mon, 10 Nov 2014 10:45:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XnmRG-0005K3-6b; Mon, 10 Nov 2014 10:43:14 +0000 Received: from mail-bn1bbn0105.outbound.protection.outlook.com ([157.56.111.105] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XnmRA-00055D-Vr for linux-arm-kernel@lists.infradead.org; Mon, 10 Nov 2014 10:43:10 +0000 Received: from DM2PR03CA0049.namprd03.prod.outlook.com (10.141.96.48) by BLUPR03MB566.namprd03.prod.outlook.com (10.141.77.155) with Microsoft SMTP Server (TLS) id 15.1.11.14; Mon, 10 Nov 2014 10:42:47 +0000 Received: from BN1BFFO11FD006.protection.gbl (2a01:111:f400:7c10::1:193) by DM2PR03CA0049.outlook.office365.com (2a01:111:e400:2428::48) with Microsoft SMTP Server (TLS) id 15.1.16.15 via Frontend Transport; Mon, 10 Nov 2014 10:42:46 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD006.mail.protection.outlook.com (10.58.144.69) with Microsoft SMTP Server (TLS) id 15.1.6.13 via Frontend Transport; Mon, 10 Nov 2014 10:42:46 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.91]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id sAAAgdaE010895; Mon, 10 Nov 2014 03:42:40 -0700 From: Minghuan Lian To: Subject: [PATCH] PCI: designware: Add support 4 ATUs assignment Date: Mon, 10 Nov 2014 18:43:25 +0800 Message-ID: <1415616205-21255-1-git-send-email-Minghuan.Lian@freescale.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(199003)(189002)(2351001)(87936001)(89996001)(87286001)(68736004)(21056001)(120916001)(50986999)(99396003)(107046002)(93916002)(88136002)(92726001)(86362001)(102836001)(19580405001)(106466001)(36756003)(44976005)(19580395003)(84676001)(77156002)(62966003)(46102003)(97736003)(50466002)(104166001)(47776003)(4396001)(20776003)(48376002)(104016003)(92566001)(50226001)(6806004)(64706001)(110136001)(95666004)(31966008)(105606002)(229853001); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB566; H:tx30smr01.am.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB566; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB566; X-Forefront-PRVS: 039178EF4A Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Minghuan.Lian@freescale.com; X-Exchange-Antispam-Report-CFA: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB566; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141110_024309_432152_D84C0B80 X-CRM114-Status: GOOD ( 13.20 ) X-Spam-Score: -0.0 (/) Cc: Bjorn Helgaas , Minghuan Lian , Hu Mingkai-B21284 , Zang Roy-R61911 , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, pcie-designware.c only supports two ATUs, ATU0 is used for CFG0 and MEM, ATU1 is used for CFG1 and IO. There is a conflict when MEM and CFG0 are accessed simultaneously. The patch adds 'num-atus' property to PCIe dts node to describe the number of PCIe controller's ATUs. If num_atus is bigger than or equal to 4, we will change ATUs assignment: ATU0 for CFG0, ATU1 for CFG1, ATU2 for MEM, ATU3 for IO. Signed-off-by: Minghuan Lian --- .../devicetree/bindings/pci/designware-pcie.txt | 1 + drivers/pci/host/pcie-designware.c | 48 ++++++++++++++++------ drivers/pci/host/pcie-designware.h | 5 +++ 3 files changed, 41 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 9f4faa8..500796e 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -26,3 +26,4 @@ Optional properties: - bus-range: PCI bus numbers covered (it is recommended for new devicetrees to specify this property, to keep backwards compatibility a range of 0x00-0xff is assumed if not present) +- num-atus: number of ATUs diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index dfed00a..b872dd0 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -48,6 +48,8 @@ #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX3 (0x3 << 0) +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) #define PCIE_ATU_CR1 0x904 @@ -346,7 +348,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) struct of_pci_range range; struct of_pci_range_parser parser; struct resource *cfg_res; - u32 val, na, ns; + u32 num_atus, val, na, ns; const __be32 *addrp; int i, index, ret; @@ -486,6 +488,18 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } } + if (of_property_read_u32(np, "num-atus", &num_atus)) + num_atus = 2; + if (num_atus >= 4) { + pp->atu_cfg0_idx = PCIE_ATU_REGION_INDEX0; + pp->atu_cfg1_idx = PCIE_ATU_REGION_INDEX1; + pp->atu_mem_idx = PCIE_ATU_REGION_INDEX2; + pp->atu_io_idx = PCIE_ATU_REGION_INDEX3; + } else { + pp->atu_cfg0_idx = pp->atu_mem_idx = PCIE_ATU_REGION_INDEX0; + pp->atu_cfg1_idx = pp->atu_io_idx = PCIE_ATU_REGION_INDEX1; + } + if (pp->ops->host_init) pp->ops->host_init(pp); @@ -511,8 +525,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp) static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) { - /* Program viewport 0 : OUTBOUND : CFG0 */ - dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, + /* Program viewport : OUTBOUND : CFG0 */ + dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | pp->atu_cfg0_idx, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE); dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE); @@ -526,8 +540,8 @@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) { - /* Program viewport 1 : OUTBOUND : CFG1 */ - dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, + /* Program viewport : OUTBOUND : CFG1 */ + dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | pp->atu_cfg1_idx, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE); @@ -541,8 +555,8 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) { - /* Program viewport 0 : OUTBOUND : MEM */ - dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, + /* Program viewport : OUTBOUND : MEM */ + dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | pp->atu_mem_idx, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE); @@ -557,8 +571,8 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) { - /* Program viewport 1 : OUTBOUND : IO */ - dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, + /* Program viewport : OUTBOUND : IO */ + dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | pp->atu_io_idx, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE); @@ -585,12 +599,14 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_viewport_cfg0(pp, busdev); ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, val); - dw_pcie_prog_viewport_mem_outbound(pp); + if (pp->atu_mem_idx == pp->atu_cfg0_idx) + dw_pcie_prog_viewport_mem_outbound(pp); } else { dw_pcie_prog_viewport_cfg1(pp, busdev); ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, val); - dw_pcie_prog_viewport_io_outbound(pp); + if (pp->atu_io_idx == pp->atu_cfg1_idx) + dw_pcie_prog_viewport_io_outbound(pp); } return ret; @@ -610,12 +626,14 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_viewport_cfg0(pp, busdev); ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, val); - dw_pcie_prog_viewport_mem_outbound(pp); + if (pp->atu_mem_idx == pp->atu_cfg0_idx) + dw_pcie_prog_viewport_mem_outbound(pp); } else { dw_pcie_prog_viewport_cfg1(pp, busdev); ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, val); - dw_pcie_prog_viewport_io_outbound(pp); + if (pp->atu_io_idx == pp->atu_cfg1_idx) + dw_pcie_prog_viewport_io_outbound(pp); } return ret; @@ -770,6 +788,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 membase; u32 memlimit; + /* set ATUs setting for MEM and IO */ + dw_pcie_prog_viewport_mem_outbound(pp); + dw_pcie_prog_viewport_io_outbound(pp); + /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index c625675..404f601 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -53,6 +53,11 @@ struct pcie_port { struct irq_domain *irq_domain; unsigned long msi_data; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); + /* ATUs setting */ + u8 atu_cfg0_idx; + u8 atu_cfg1_idx; + u8 atu_mem_idx; + u8 atu_io_idx; }; struct pcie_host_ops {