| Message ID | 1416406451-4578-4-git-send-email-yingjoe.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Nov 19 2014 at 2:14:10 pm GMT, Yingjoe Chen <yingjoe.chen@mediatek.com> wrote: > Add sysirq settings for mt6589/mt8135/mt8127 > This also correct timer interrupt flag. The old setting works > because boot loader already set polarity for timer interrupt. > Without intpol support, the setting was not changed so gic > can get the irq correctly. > > Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > --- > arch/arm/boot/dts/mt6589.dtsi | 14 ++++++++++++-- > arch/arm/boot/dts/mt8127.dtsi | 14 ++++++++++++-- > arch/arm/boot/dts/mt8135.dtsi | 14 ++++++++++++-- > 3 files changed, 36 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi > index e3c7600..c91b2a9 100644 > --- a/arch/arm/boot/dts/mt6589.dtsi > +++ b/arch/arm/boot/dts/mt6589.dtsi > @@ -19,7 +19,7 @@ > > / { > compatible = "mediatek,mt6589"; > - interrupt-parent = <&gic>; > + interrupt-parent = <&sysirq>; This worries me a bit. Your sysirq cannot handle PPIs, and yet you make it the top-level interrupt controller, without amending any PPI. Does it mean you do not use *any* PPI? No per-cpu timer, nothing? Thanks, M.
On Wed, 2014-11-19 at 17:49 +0000, Marc Zyngier wrote: > On Wed, Nov 19 2014 at 2:14:10 pm GMT, Yingjoe Chen <yingjoe.chen@mediatek.com> wrote: > > Add sysirq settings for mt6589/mt8135/mt8127 > > This also correct timer interrupt flag. The old setting works > > because boot loader already set polarity for timer interrupt. > > Without intpol support, the setting was not changed so gic > > can get the irq correctly. > > > > Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > > --- > > arch/arm/boot/dts/mt6589.dtsi | 14 ++++++++++++-- > > arch/arm/boot/dts/mt8127.dtsi | 14 ++++++++++++-- > > arch/arm/boot/dts/mt8135.dtsi | 14 ++++++++++++-- > > 3 files changed, 36 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi > > index e3c7600..c91b2a9 100644 > > --- a/arch/arm/boot/dts/mt6589.dtsi > > +++ b/arch/arm/boot/dts/mt6589.dtsi > > @@ -19,7 +19,7 @@ > > > > / { > > compatible = "mediatek,mt6589"; > > - interrupt-parent = <&gic>; > > + interrupt-parent = <&sysirq>; > > This worries me a bit. Your sysirq cannot handle PPIs, and yet you make > it the top-level interrupt controller, without amending any PPI. > > Does it mean you do not use *any* PPI? No per-cpu timer, nothing? Matthias had a patch to enable arch timer[1], but that is not merged yet. Node using PPI interrupts must add their own interrupt-parent. This works if we don't have node that use both PPI & SPI interrupts. For timer, we could do this: + timer2: timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <13000000>; + }; [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/277017.html Joe.C
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index e3c7600..c91b2a9 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -19,7 +19,7 @@ / { compatible = "mediatek,mt6589"; - interrupt-parent = <&gic>; + interrupt-parent = <&sysirq>; cpus { #address-cells = <1>; @@ -76,15 +76,25 @@ timer: timer@10008000 { compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; - interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; clocks = <&system_clk>, <&rtc_clk>; clock-names = "system-clk", "rtc-clk"; }; + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6589-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; #interrupt-cells = <3>; + interrupt-parent = <&gic>; reg = <0x10211000 0x1000>, <0x10212000 0x1000>, <0x10214000 0x2000>, diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi index c3ee060..49f5976 100644 --- a/arch/arm/boot/dts/mt8127.dtsi +++ b/arch/arm/boot/dts/mt8127.dtsi @@ -18,7 +18,7 @@ / { compatible = "mediatek,mt8127"; - interrupt-parent = <&gic>; + interrupt-parent = <&sysirq>; cpus { #address-cells = <1>; @@ -82,15 +82,25 @@ compatible = "mediatek,mt8127-timer", "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x80>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; clocks = <&system_clk>, <&rtc_clk>; clock-names = "system-clk", "rtc-clk"; }; + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt8127-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200100 0 0x1c>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; #interrupt-cells = <3>; + interrupt-parent = <&gic>; reg = <0 0x10211000 0 0x1000>, <0 0x10212000 0 0x1000>, <0 0x10214000 0 0x2000>, diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 5faae6e..60338d9 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -18,7 +18,7 @@ / { compatible = "mediatek,mt8135"; - interrupt-parent = <&gic>; + interrupt-parent = <&sysirq>; cpu-map { cluster0 { @@ -105,15 +105,25 @@ compatible = "mediatek,mt8135-timer", "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x80>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; clocks = <&system_clk>, <&rtc_clk>; clock-names = "system-clk", "rtc-clk"; }; + sysirq: interrupt-controller@10200030 { + compatible = "mediatek,mt8135-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200030 0 0x1c>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + interrupt-parent = <&gic>; reg = <0 0x10211000 0 0x1000>, <0 0x10212000 0 0x1000>, <0 0x10214000 0 0x2000>,
Add sysirq settings for mt6589/mt8135/mt8127 This also correct timer interrupt flag. The old setting works because boot loader already set polarity for timer interrupt. Without intpol support, the setting was not changed so gic can get the irq correctly. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> --- arch/arm/boot/dts/mt6589.dtsi | 14 ++++++++++++-- arch/arm/boot/dts/mt8127.dtsi | 14 ++++++++++++-- arch/arm/boot/dts/mt8135.dtsi | 14 ++++++++++++-- 3 files changed, 36 insertions(+), 6 deletions(-)