From patchwork Wed Nov 19 15:52:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5338421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B3A839F2F1 for ; Wed, 19 Nov 2014 15:55:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D8947201CD for ; Wed, 19 Nov 2014 15:55:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2ACF20176 for ; Wed, 19 Nov 2014 15:55:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xr7ZK-0006f8-QO; Wed, 19 Nov 2014 15:53:22 +0000 Received: from mail-wi0-f178.google.com ([209.85.212.178]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xr7Z1-0006Mi-MG for linux-arm-kernel@lists.infradead.org; Wed, 19 Nov 2014 15:53:04 +0000 Received: by mail-wi0-f178.google.com with SMTP id hi2so2357179wib.11 for ; Wed, 19 Nov 2014 07:52:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=K0NuKOD0guOXidYxNDI3jyJvf4EZkKv8pGSvtGFsEX4=; b=LWKRnzHS/+xcG5vNqn3oXV7MA7hKhm7bWDqcXrTy3BsN5qcaXx3l1xh86BY+i6KlUU pjbOVUq+5JxHfPuGyISkAS+yOgAgwRSYsEKmGh7IXsIWiLBsZ11DV35s3vWD8AWe4i8y viIkSKkWvz1nTJ5FxP1UAF5G2Z0TXpIbc7pP5wInqXNvJHQ7E0JpUjnFQRxocvBPJjhN EXmjsMbHUQoD9x7g7G0NZ2gy4OplhL46X6LITkIT8twRUfEpF4GK6AF3ue/thB34SZyf psnNVXrSQWNrhjeEjOQ+7TEd1pmGGBcm5NFbX/RqQttuz22jN/Yx7nUo9jc5xTKgWfCp 4SXg== X-Gm-Message-State: ALoCoQlViH2CiGv8k9tn3hxmrcSS9P1zcXcRAk42j+lyt3VKht3TAZdHbR2/MY6mAy1U0As4rW9l X-Received: by 10.180.72.199 with SMTP id f7mr14185792wiv.53.1416412361241; Wed, 19 Nov 2014 07:52:41 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id j17sm2797482wjn.32.2014.11.19.07.52.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Nov 2014 07:52:40 -0800 (PST) From: Daniel Thompson To: Will Deacon , Russell King Subject: [PATCH] arm: perf: Prevent wraparound during overflow Date: Wed, 19 Nov 2014 15:52:26 +0000 Message-Id: <1416412346-8759-1-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141119_075303_879797_66671589 X-CRM114-Status: GOOD ( 15.11 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Peter Zijlstra , patches@linaro.org, linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Ingo Molnar , Paul Mackerras , John Stultz , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the overflow threshold for a counter is set above or near the 0xffffffff boundary then the kernel may lose track of the overflow causing only events that occur *after* the overflow to be recorded. Specifically the problem occurs when the value of the performance counter overtakes its original programmed value due to wrap around. Typical solutions to this problem are either to avoid programming in values likely to be overtaken or to treat the overflow bit as the 33rd bit of the counter. Its somewhat fiddly to refactor the code to correctly handle the 33rd bit during irqsave sections (context switches for example) so instead we take the simpler approach of avoiding values likely to be overtaken. We set the limit to half of max_period because this matches the limit imposed in __hw_perf_event_init(). This causes a doubling of the interrupt rate for large threshold values, however even with a very fast counter ticking at 4GHz the interrupt rate would only be ~1Hz. Signed-off-by: Daniel Thompson --- Notes: There is similar code in the arm64 tree which retains the assumptions of the original arm code regarding 32-bit wide performance counters. If this patch doesn't get beaten up during review I'll also share a similar patch for arm64. arch/arm/kernel/perf_event.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 1.9.3 diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 266cba46db3e..b50a770f8c99 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -115,8 +115,14 @@ int armpmu_event_set_period(struct perf_event *event) ret = 1; } - if (left > (s64)armpmu->max_period) - left = armpmu->max_period; + /* + * Limit the maximum period to prevent the counter value + * from overtaking the one we are about to program. In + * effect we are reducing max_period to account for + * interrupt latency (and we are being very conservative). + */ + if (left > (s64)(armpmu->max_period >> 1)) + left = armpmu->max_period >> 1; local64_set(&hwc->prev_count, (u64)-left);