From patchwork Thu Nov 20 05:01:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 5345721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 01B6C9F387 for ; Thu, 20 Nov 2014 05:05:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0A02E2020E for ; Thu, 20 Nov 2014 05:05:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B6A2201F5 for ; Thu, 20 Nov 2014 05:05:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrJsg-0007Pz-Dx; Thu, 20 Nov 2014 05:02:10 +0000 Received: from gate2.alliedtelesis.co.nz ([2001:df5:b000:5::4]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrJsc-0007PW-QK for linux-arm-kernel@lists.infradead.org; Thu, 20 Nov 2014 05:02:08 +0000 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id B6A9B844DA; Thu, 20 Nov 2014 18:01:36 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1416459696; bh=WMC/4GRslicD30vI1TcDJZZgelXiKCIeuD6AWGV4QSE=; h=From:To:Cc:Subject:Date; b=YuaOrX20PVRFt2YbMRkDwWsbPD77kbZWpj3plMdx2YtX5WdNyolnbxL0Lj5qPVsIH tw4hKM9Kj+ngD/58F078bpHxeEzYZS/Jpie44gJDT4SwUmipkkwdzhcwSMsblauC2A GZIfhx9n6oME2CSAEJHKGuPHrwVSORUNgpvOsuUI= Received: from alliedtelesyn.co.nz (Not Verified[10.32.16.32]) by mmarshal3.atlnz.lc with MailMarshal (v7, 1, 0, 4874) id ; Thu, 20 Nov 2014 18:01:36 +1300 Received: from MAIL/SpoolDir by alliedtelesyn.co.nz (Mercury 1.48); 20 Nov 14 18:02:06 +1300 Received: from SpoolDir by MAIL (Mercury 1.48); 20 Nov 14 18:01:59 +1300 Received: from chrisp-dl.ws.atlnz.lc (10.33.22.20) by alliedtelesyn.co.nz (Mercury 1.48) with ESMTP; 20 Nov 14 18:01:54 +1300 Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id D4B05C0CB4; Thu, 20 Nov 2014 18:01:23 +1300 (NZDT) From: Chris Packham To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH] clk: mvebu: armada-xp: Support for MSYS SoC Date: Thu, 20 Nov 2014 18:01:19 +1300 Message-Id: <1416459679-30944-1-git-send-email-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.2.0.rc0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141119_210207_443076_84D7E411 X-CRM114-Status: GOOD ( 13.86 ) X-Spam-Score: -0.1 (/) Cc: Thomas Petazzoni , Andrew Lunn , Chris Packham , Gregory Clement , Marcin Wojtas , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_LOW, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The MSYS SoCs are a range of packet processors with integrated CPUs based on armada-xp. One difference is that the TCLK frequency is fixed at 200MHz as opposed to the fixed 250MHz used on armada-xp. The clock-gating options are a subset of what's available on the armada-xp so this code should be compatible. Signed-off-by: Chris Packham --- Hi, This patch is enough to get the uart clock dividers correct so I get some output. As far as I've been able to tell there is no way of dynamically detecting the TCLK frequency. The core clock frequency and ratio calculations are probably not correct but for these CPU inside a packet processor systems I'm not sure how much that actually matter since these systems aren't likely to do any kind of dynamic frequency scaling. Thansk, Chris drivers/clk/mvebu/armada-xp.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c index b309431..9f852f8 100644 --- a/drivers/clk/mvebu/armada-xp.c +++ b/drivers/clk/mvebu/armada-xp.c @@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar) return 250000000; } +/* MSYS TCLK frequency is fixed to 200MHz */ +static u32 __init msys_get_tclk_freq(void __iomem *sar) +{ + return 200000000; +} + static const u32 axp_cpu_freqs[] __initconst = { 1000000000, 1066000000, @@ -158,6 +164,14 @@ static const struct coreclk_soc_desc axp_coreclks = { .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), }; +static const struct coreclk_soc_desc msys_coreclks = { + .get_tclk_freq = msys_get_tclk_freq, + .get_cpu_freq = axp_get_cpu_freq, + .get_clk_ratio = axp_get_clk_ratio, + .ratios = axp_coreclk_ratios, + .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), +}; + /* * Clock Gating Control */ @@ -200,9 +214,13 @@ static void __init axp_clk_init(struct device_node *np) struct device_node *cgnp = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock"); - mvebu_coreclk_setup(np, &axp_coreclks); + if (of_device_is_compatible(np, "marvell,msys-core-clock")) + mvebu_coreclk_setup(np, &msys_coreclks); + else + mvebu_coreclk_setup(np, &axp_coreclks); if (cgnp) mvebu_clk_gating_setup(cgnp, axp_gating_desc); } CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init); +CLK_OF_DECLARE(msys_clk, "marvell,msys-core-clock", axp_clk_init);