From patchwork Fri Nov 21 14:53:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5355431 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0C71C11AC for ; Fri, 21 Nov 2014 14:56:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05491200E0 for ; Fri, 21 Nov 2014 14:56:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CFB2320145 for ; Fri, 21 Nov 2014 14:56:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrpbM-0001Y8-0r; Fri, 21 Nov 2014 14:54:24 +0000 Received: from mail-wg0-f51.google.com ([74.125.82.51]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrpbI-0001Uu-2V for linux-arm-kernel@lists.infradead.org; Fri, 21 Nov 2014 14:54:21 +0000 Received: by mail-wg0-f51.google.com with SMTP id k14so6638395wgh.24 for ; Fri, 21 Nov 2014 06:53:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bXXaBzXUPbdrynBbegiz5JLnR6T608x/Xn3zCWfEhGA=; b=iYv8q2zO2QxSCxm1122hCQLI/yNA7zr3mhuVDPcsd9YiJYyRmYkYHMXzn4sMo4cttZ TDH12yVp+lRo85On+QjfyVHOOna8Rpjr1MrtV0QSP9f4K8jkyeNiLlFD80FEaJf0X3Ev Os8X3q4RnVgKL/VvQ8KQ9VhvGOXu7nfq2teazS+TmrjTLYu0WPdftCbYWBVS8cEZZTwm aQHs71G07smbWr4i3ILd62Px/tZfx/TXW8lOF+OfE8ge9H+TQmLgLJM2K8OGaLudsuii MMYhjKGiNxoDkxDkjcPEKpT/g2wXFAhUt+Aohr0YyIK41umFfqoXlhZiaP2GSIx9M4nX itcg== X-Gm-Message-State: ALoCoQm3+z7XHutD6eTbMMdkPMw1U9ORU2vyaIfjs5mDONgEUGO3iqftenQ3kogbdKa/4PbLW52f X-Received: by 10.194.185.167 with SMTP id fd7mr8573556wjc.108.1416581633197; Fri, 21 Nov 2014 06:53:53 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id r10sm9049124wiy.19.2014.11.21.06.53.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Nov 2014 06:53:52 -0800 (PST) From: Daniel Thompson To: Russell King , Will Deacon Subject: [PATCH] arm: perf: Directly handle SMP platforms with one SPI Date: Fri, 21 Nov 2014 14:53:23 +0000 Message-Id: <1416581603-30557-1-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141121_065420_423338_F79FF27E X-CRM114-Status: GOOD ( 24.45 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Peter Zijlstra , patches@linaro.org, Linus Walleij , linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Ingo Molnar , Paul Mackerras , Sascha Hauer , John Stultz , Thomas Gleixner , Shawn Guo , Sumit Semwal , linux-arm-kernel@lists.infradead.org, Lucas Stach X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some ARM platforms mux the PMU interrupt of every core into a single SPI. On such platforms if the PMU of any core except 0 raises an interrupt then it cannot be serviced and eventually, if you are lucky, the spurious irq detection might forcefully disable the interrupt. On these SoCs it is not possible to determine which core raised the interrupt so workaround this issue by queuing irqwork on the other cores whenever the primary interrupt handler is unable to service the interrupt. The u8500 platform has an alternative workaround that dynamically alters the affinity of the PMU interrupt. This workaround logic is no longer required so the original code is removed as is the hook it relied upon. Tested on imx6q (which has fours cores/PMUs all muxed to a single SPI). Signed-off-by: Daniel Thompson Tested-by: Linus Walleij --- Notes: Thanks to Lucas Stach, Russell King and Thomas Gleixner for critiquing an older, completely different way to tackle the same problem. arch/arm/include/asm/pmu.h | 10 +++++ arch/arm/kernel/perf_event.c | 11 ++--- arch/arm/kernel/perf_event_cpu.c | 94 ++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-ux500/cpu-db8500.c | 29 ------------- 4 files changed, 107 insertions(+), 37 deletions(-) -- 1.9.3 diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index 0b648c541293..36472c3cc283 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h @@ -81,6 +81,12 @@ struct pmu_hw_events { raw_spinlock_t pmu_lock; }; +struct arm_pmu_work { + struct irq_work work; + struct arm_pmu *arm_pmu; + atomic_t ret; +}; + struct arm_pmu { struct pmu pmu; cpumask_t active_irqs; @@ -101,6 +107,7 @@ struct arm_pmu { void (*reset)(void *); int (*request_irq)(struct arm_pmu *, irq_handler_t handler); void (*free_irq)(struct arm_pmu *); + irqreturn_t (*handle_irq_none)(struct arm_pmu *); int (*map_event)(struct perf_event *event); int num_events; atomic_t active_events; @@ -108,6 +115,9 @@ struct arm_pmu { u64 max_period; struct platform_device *plat_device; struct pmu_hw_events *(*get_hw_events)(void); + int single_irq; + struct arm_pmu_work __percpu *work; + atomic_t remaining_work; }; #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index b50a770f8c99..0792c913b9bb 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -306,22 +306,17 @@ validate_group(struct perf_event *event) static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) { struct arm_pmu *armpmu; - struct platform_device *plat_device; - struct arm_pmu_platdata *plat; int ret; u64 start_clock, finish_clock; if (irq_is_percpu(irq)) dev = *(void **)dev; armpmu = dev; - plat_device = armpmu->plat_device; - plat = dev_get_platdata(&plat_device->dev); start_clock = sched_clock(); - if (plat && plat->handle_irq) - ret = plat->handle_irq(irq, dev, armpmu->handle_irq); - else - ret = armpmu->handle_irq(irq, dev); + ret = armpmu->handle_irq(irq, dev); + if (ret == IRQ_NONE && armpmu->handle_irq_none) + ret = armpmu->handle_irq_none(dev); finish_clock = sched_clock(); perf_sample_event_took(finish_clock - start_clock); diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index eb2c4d55666b..e7153dc3b489 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -88,6 +88,75 @@ static void cpu_pmu_disable_percpu_irq(void *data) disable_percpu_irq(irq); } +/* + * Workaround logic that is distributed to all cores if the PMU has only + * a single IRQ and the CPU receiving that IRQ cannot handle it. Its + * job is to try to service the interrupt on the current CPU. It will + * also enable the IRQ again if all the other CPUs have already tried to + * service it. + */ +static void cpu_pmu_do_percpu_work(struct irq_work *w) +{ + struct arm_pmu_work *work = container_of(w, struct arm_pmu_work, work); + struct arm_pmu *cpu_pmu = work->arm_pmu; + + atomic_set(&work->ret, + cpu_pmu->handle_irq(cpu_pmu->single_irq, cpu_pmu)); + + if (atomic_dec_and_test(&cpu_pmu->remaining_work)) + enable_irq(cpu_pmu->single_irq); +} + +/* + * This callback, which is enabled only on SMP platforms that are + * running with a single IRQ, is called when the PMU handler running in + * the current CPU cannot service the interrupt. + * + * It will disable the interrupt and distribute irqwork to all other + * processors in the system. Hopefully one of them will clear the + * interrupt... + */ +static irqreturn_t cpu_pmu_handle_irq_none(struct arm_pmu *cpu_pmu) +{ + int num_online = num_online_cpus(); + irqreturn_t ret = IRQ_NONE; + int cpu, cret; + + if (num_online <= 1) + return IRQ_NONE; + + disable_irq_nosync(cpu_pmu->single_irq); + atomic_add(num_online, &cpu_pmu->remaining_work); + smp_mb__after_atomic(); + + for_each_online_cpu(cpu) { + struct arm_pmu_work *work = per_cpu_ptr(cpu_pmu->work, cpu); + + if (cpu == smp_processor_id()) + continue; + + /* + * We can be extremely relaxed about memory ordering + * here. All we are doing is gathering information + * about the past to help us give a return value that + * will keep the spurious interrupt detector both happy + * *and* functional. We are not shared so we can + * tolerate the occasional spurious IRQ_HANDLED. + */ + cret = atomic_read(&work->ret); + if (cret != IRQ_NONE) + ret = cret; + + if (!irq_work_queue_on(&work->work, cpu)) + atomic_dec(&cpu_pmu->remaining_work); + } + + if (atomic_dec_and_test(&cpu_pmu->remaining_work)) + enable_irq(cpu_pmu->single_irq); + + return ret; +} + static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu) { int i, irq, irqs; @@ -107,6 +176,9 @@ static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu) if (irq >= 0) free_irq(irq, cpu_pmu); } + + cpu_pmu->handle_irq_none = cpu_pmu_handle_irq_none; + free_percpu(cpu_pmu->work); } } @@ -162,6 +234,28 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler) cpumask_set_cpu(i, &cpu_pmu->active_irqs); } + + /* + * If we are running SMP and have only one interrupt source + * then get ready to share that single irq among the cores. + */ + if (nr_cpu_ids > 1 && irqs == 1) { + cpu_pmu->single_irq = platform_get_irq(pmu_device, 0); + cpu_pmu->work = alloc_percpu(struct arm_pmu_work); + if (!cpu_pmu->work) { + pr_err("no memory for shared IRQ workaround\n"); + return -ENOMEM; + } + + for_each_possible_cpu(i) { + struct arm_pmu_work *w = + per_cpu_ptr(cpu_pmu->work, i); + init_irq_work(&w->work, cpu_pmu_do_percpu_work); + w->arm_pmu = cpu_pmu; + } + + cpu_pmu->handle_irq_none = cpu_pmu_handle_irq_none; + } } return 0; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 6f63954c8bde..917774999c5c 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include #include @@ -23,7 +21,6 @@ #include #include -#include #include #include "setup.h" @@ -99,30 +96,6 @@ static void __init u8500_map_io(void) iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); } -/* - * The PMU IRQ lines of two cores are wired together into a single interrupt. - * Bounce the interrupt to the other core if it's not ours. - */ -static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) -{ - irqreturn_t ret = handler(irq, dev); - int other = !smp_processor_id(); - - if (ret == IRQ_NONE && cpu_online(other)) - irq_set_affinity(irq, cpumask_of(other)); - - /* - * We should be able to get away with the amount of IRQ_NONEs we give, - * while still having the spurious IRQ detection code kick in if the - * interrupt really starts hitting spuriously. - */ - return ret; -} - -static struct arm_pmu_platdata db8500_pmu_platdata = { - .handle_irq = db8500_pmu_handler, -}; - static const char *db8500_read_soc_id(void) { void __iomem *uid = __io_address(U8500_BB_UID_BASE); @@ -143,8 +116,6 @@ static struct device * __init db8500_soc_device_init(void) } static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { - /* Requires call-back bindings. */ - OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), /* Requires DMA bindings. */ OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, "ux500-msp-i2s.0", &msp0_platform_data),