diff mbox

[v10,10/10] arm: dts: qcom: Add idle state device nodes for 8064

Message ID 1416593037-27527-11-git-send-email-lina.iyer@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Lina Iyer Nov. 21, 2014, 6:03 p.m. UTC
Add ARM common idle state device bindings for cpuidle support for APQ
8064.

Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Stephen Boyd Nov. 26, 2014, 8:18 p.m. UTC | #1
On 11/21/2014 10:03 AM, Lina Iyer wrote:
> Add ARM common idle state device bindings for cpuidle support for APQ
> 8064.
>
> Support Standby and Standalone power collapse (power down that does not
> affect any SoC idle states) for each cpu.
>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>

With nitpick addressed:

Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>

> @@ -53,12 +56,30 @@
>   			next-level-cache = <&L2>;
>   			qcom,acc = <&acc3>;
>   			qcom,saw = <&saw3>;
> +			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
>   		};
>   
>   		L2: l2-cache {
>   			compatible = "cache";
>   			cache-level = <2>;
>   		};
> +
> +		idle-states {
> +			CPU_STBY: standby {
> +				compatible = "qcom,idle-state-stby", "arm,idle-state";
> +				entry-latency-us = <1>;
> +				exit-latency-us = <1>;
> +				min-residency-us = <2>;
> +			};
> +
> +			CPU_SPC: spc {
> +				compatible = "qcom,idle-state-spc", "arm,idle-state";
> +				entry-latency-us = <400>;
> +				exit-latency-us = <900>;
> +				min-residency-us = <3000>;
> +			};
> +		};
> +

Nitpick, no need for blank line here.

>   	};
>   
>   	cpu-pmu {
diff mbox

Patch

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 9fd24bc..3eaf242 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@ 
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@1 {
@@ -33,6 +34,7 @@ 
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@2 {
@@ -43,6 +45,7 @@ 
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@3 {
@@ -53,12 +56,30 @@ 
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		L2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
 		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby", "arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;
+			};
+
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc", "arm,idle-state";
+				entry-latency-us = <400>;
+				exit-latency-us = <900>;
+				min-residency-us = <3000>;
+			};
+		};
+
 	};
 
 	cpu-pmu {