From patchwork Mon Nov 24 22:18:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Jarzmik X-Patchwork-Id: 5370251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8D3EAC11AC for ; Mon, 24 Nov 2014 22:21:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BAA3B2012D for ; Mon, 24 Nov 2014 22:21:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C03182010C for ; Mon, 24 Nov 2014 22:21:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xt1yx-0000Hl-K2; Mon, 24 Nov 2014 22:19:43 +0000 Received: from smtp02.smtpout.orange.fr ([80.12.242.124] helo=smtp.smtpout.orange.fr) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xt1yu-0007ZY-7L for linux-arm-kernel@lists.infradead.org; Mon, 24 Nov 2014 22:19:40 +0000 Received: from beldin.home ([109.222.88.20]) by mwinf5d49 with ME id KaKH1p0020SLQZp03aKHC2; Mon, 24 Nov 2014 23:19:18 +0100 X-ME-Helo: beldin.home X-ME-Date: Mon, 24 Nov 2014 23:19:18 +0100 X-ME-IP: 109.222.88.20 From: Robert Jarzmik To: Daniel Mack , Haojian Zhuang , Robert Jarzmik , Russell King , Rob Herring , Marc Zyngier , Dmitry Eremin-Solenikov Subject: [PATCH] ARM: pxa: arbitrarily set first interrupt number Date: Mon, 24 Nov 2014 23:18:22 +0100 Message-Id: <1416867502-6877-1-git-send-email-robert.jarzmik@free.fr> X-Mailer: git-send-email 2.1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141124_141940_443205_6B2B12F5 X-CRM114-Status: UNSURE ( 8.82 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As IRQ0, the legacy timer interrupt should not be used as an interrupt number, shift the interrupts by a fixed number. As we had in a special case a shift of 16 when ISA bus was used on a PXA, use that value as the first interrupt number, regardless of ISA or not. Signed-off-by: Robert Jarzmik --- arch/arm/mach-pxa/Kconfig | 5 ----- arch/arm/mach-pxa/include/mach/irqs.h | 9 ++------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index e6690a4..bfca4ead 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -73,14 +73,12 @@ config ARCH_VIPER select I2C_GPIO if I2C=y select ISA select PXA25x - select PXA_HAVE_ISA_IRQS config MACH_ARCOM_ZEUS bool "Arcom/Eurotech ZEUS SBC" select ARCOM_PCMCIA select ISA select PXA27x - select PXA_HAVE_ISA_IRQS config MACH_BALLOON3 bool "Balloon 3 board" @@ -680,9 +678,6 @@ config SHARPSL_PM_MAX1111 select SPI select SPI_MASTER -config PXA_HAVE_ISA_IRQS - bool - config PXA310_ULPI bool diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 48c2fd8..83e04d4 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -12,14 +12,9 @@ #ifndef __ASM_MACH_IRQS_H #define __ASM_MACH_IRQS_H -#ifdef CONFIG_PXA_HAVE_ISA_IRQS -#define PXA_ISA_IRQ(x) (x) -#define PXA_ISA_IRQ_NUM (16) -#else -#define PXA_ISA_IRQ_NUM (0) -#endif +#include -#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) +#define PXA_IRQ(x) (NR_IRQS_LEGACY + (x)) #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */