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Wed, 26 Nov 2014 20:19:08 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, mturquette@linaro.org Subject: [PATCH 4/4] clk: samsung: add cpu clock configuration data and instantiate cpu clock Date: Wed, 26 Nov 2014 16:47:51 +0530 Message-id: <1417000671-11996-5-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1417000671-11996-1-git-send-email-a.kesavan@samsung.com> References: <1417000671-11996-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMLMWRmVeSWpSXmKPExsWyRsSkWld3e2mIQd8hFos1f5UsNj2+xmox 4/w+JounEy6yWRx+085qsWrXH0YHNo+ds+6ye9y5tofNY/OSeo++LasYPT5vkgtgjeKySUnN ySxLLdK3S+DKeL/gCUvBTvmK+xvPsTQwLpLqYuTkkBAwkXjwYTUrhC0mceHeerYuRi4OIYGl jBK7zj9gginqWtDIBmILCUxnlGj+zAFR1Mck8fjlQbBuNgE9iQX/vjKD2CICBRKnZ84As5kF HCVWfZ8LNkhYIF7i9JP/YPUsAqoSh282sYDYvAKuEj0dq4AWcAAtU5CYM8kGJMwp4CaxYvs6 Foi9rhL3jj0GO05CoJtd4vXjNiaIOQIS3yYfYoHolZXYdIAZ4mZJiYMrbrBMYBRewMiwilE0 tSC5oDgpvchErzgxt7g0L10vOT93EyMwrE//ezZhB+O9A9aHGAU4GJV4eCOkSkOEWBPLiitz DzGaAm2YyCwlmpwPjJ68knhDYzMjC1MTU2Mjc0szJXHe11I/g4UE0hNLUrNTUwtSi+KLSnNS iw8xMnFwSjUwOr/VMDtsPGFz3mHJMu583UNf6qTVAowOLI3g6ElYdD738eStbCz/Nk74e7hc RoO7wzbuodn6uKfm5zMFH9360MwjXZGR9yDoQYKk2Be7c9l7FmZdujZz8gX21WETn+zcV2Yi kL0nje8BR8+PWS8uLc2e4Wai8eHCt/Cys4kH4/I5rKQdlG7LKbEUZyQaajEXFScCAGrtPW5m AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLIsWRmVeSWpSXmKPExsVy+t9jQV2d7aUhBuubLC3W/FWy2PT4GqvF jPP7mCyeTrjIZnH4TTurxapdfxgd2Dx2zrrL7nHn2h42j81L6j36tqxi9Pi8SS6ANaqB0SYj NTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6AAlhbLEnFKg UEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8b7BU9YCnbKV9zfeI6lgXGRVBcjJ4eE gIlE14JGNghbTOLCvfVgtpDAdEaJ5s8cXYxcQHYfk8TjlwdZQRJsAnoSC/59ZQaxRQQKJE7P nAFmMws4Sqz6PpcJxBYWiJc4/eQ/WD2LgKrE4ZtNLCA2r4CrRE/HKqAFHEDLFCTmTLIBCXMK uEms2L6OBWKvq8S9Y4/ZJjDyLmBkWMUomlqQXFCclJ5rpFecmFtcmpeul5yfu4kRHDXPpHcw rmqwOMQowMGoxMMbIVUaIsSaWFZcmXuIUYKDWUmE9+sGoBBvSmJlVWpRfnxRaU5q8SFGU6Cj JjJLiSbnAyM6ryTe0NjE3NTY1NLEwsTMUkmc98bN3BAhgfTEktTs1NSC1CKYPiYOTqkGRu6t DSdar5pNvrdAaS9rDO/07InMUQ6/Vm7c4+nCohdy4/2Hp48PK0/8sKpwn9WJB7P7A16q2YhO XfA4JTBjffabPRebGja1yWUVcilKzz0x67+wmEZhyhl2v+83Lr/2zPljHSrOcfH2YfMWFjd5 3etSs3YdvDVrQtjHrswNJ+3Y3i5gsQOmOCWW4oxEQy3mouJEAFH0xDWwAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141126_031930_849367_5ECA33FF X-CRM114-Status: GOOD ( 11.64 ) X-Spam-Score: -5.0 (-----) Cc: kesavan.abhilash@gmail.com, linux-samsung-soc@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the Atlas CPU clock configuration data and instantiate the CPU clock type for Exynos7. Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-cpu.h | 5 +++++ drivers/clk/samsung/clk-exynos7.c | 28 +++++++++++++++++++++++++++- include/dt-bindings/clock/exynos7-clk.h | 3 ++- 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 24e844e..1fd7f51 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -31,6 +31,11 @@ #define E5420_KFC_DIV(kpll, pclk, aclk) \ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) +#define EXYNOS7_ATL_DIV0(aclk, pclk, atclk, pclk_dbg) \ + ((aclk << 8) | (pclk << 12) | (atclk << 20) | (pclk_dbg << 26)) +#define EXYNOS7_ATL_DIV1(pll, hpm, cntclk) \ + ((pll << 0) | (hpm << 4) | (cntclk << 8)) + /** * struct exynos_cpuclk_data: config data to setup cpu clocks. * @prate: frequency of the primary parent clock (in KHz). diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 78f66b4..dc9b7fb 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -14,6 +14,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #include /* Register Offset definitions for CMU_TOPC (0x10570000) */ @@ -63,6 +64,25 @@ static const struct samsung_pll_rate_table pll1450x_24mhz_tbl[] = { PLL_35XX_RATE(200000000, 200, 3, 3), }; +static const struct exynos_cpuclk_cfg_data exynos7_atlclk_d[] __initconst = { + { 1600000, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), }, + { 1500000, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), }, + { 1400000, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), }, + { 1300000, EXYNOS7_ATL_DIV0(2, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), }, + { 1200000, EXYNOS7_ATL_DIV0(1, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), }, + { 1100000, EXYNOS7_ATL_DIV0(1, 7, 7, 7), EXYNOS7_ATL_DIV1(1, 2, 7), }, + { 1000000, EXYNOS7_ATL_DIV0(1, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 2, 6), }, + { 900000, EXYNOS7_ATL_DIV0(1, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 2, 6), }, + { 800000, EXYNOS7_ATL_DIV0(1, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 2, 5), }, + { 700000, EXYNOS7_ATL_DIV0(1, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 2, 5), }, + { 600000, EXYNOS7_ATL_DIV0(1, 4, 4, 4), EXYNOS7_ATL_DIV1(1, 2, 4), }, + { 500000, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), }, + { 400000, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), }, + { 300000, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), }, + { 200000, EXYNOS7_ATL_DIV0(1, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), }, + { 0 }, +}; + static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), FFACTOR(0, "ffac_topc_bus0_pll_div4", @@ -518,7 +538,13 @@ static struct samsung_cmu_info atlas_cmu_info __initdata = { static void __init exynos7_clk_atlas_init(struct device_node *np) { - samsung_cmu_register_one(np, &atlas_cmu_info); + struct samsung_clk_provider *ctx; + + ctx = samsung_cmu_register_one(np, &atlas_cmu_info); + exynos_register_cpu_clock(ctx, CLK_ATLAS_CLK, "atlclk", + mout_atlas_p[0], mout_atlas_p[1], 0x0, + exynos7_atlclk_d, ARRAY_SIZE(exynos7_atlclk_d), + CLK_CPU_HAS_DIV1, np); } CLK_OF_DECLARE(exynos7_clk_atlas, "samsung,exynos7-clock-atlas", diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 93c78f9..33bc166 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -55,7 +55,8 @@ #define CLK_ATLAS 12 #define DOUT_SCLK_HPM_ATLAS 13 #define DOUT_ATLAS_PLL 14 -#define ATLAS_NR_CLK 15 +#define CLK_ATLAS_CLK 15 +#define ATLAS_NR_CLK 16 /* CCORE */ #define PCLK_RTC 1