From patchwork Wed Nov 26 13:34:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jungseung Lee X-Patchwork-Id: 5385461 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 19F14C11AC for ; Wed, 26 Nov 2014 13:36:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 17E6B2010C for ; Wed, 26 Nov 2014 13:36:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 24FC9200DB for ; Wed, 26 Nov 2014 13:36:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xtck2-0005C6-Cb; Wed, 26 Nov 2014 13:34:46 +0000 Received: from mail-pd0-x236.google.com ([2607:f8b0:400e:c02::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xtcjw-00041c-SZ for linux-arm-kernel@lists.infradead.org; Wed, 26 Nov 2014 13:34:41 +0000 Received: by mail-pd0-f182.google.com with SMTP id r10so2843126pdi.13 for ; Wed, 26 Nov 2014 05:34:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=rxxtorNA80/ga2RXK68AodTYOKbii2mB83tppoq4AY8=; b=nV6Lnm3CoYGmKRLeNUZRqanSKdYeq1G+quKh9sVTwHyN9M2UxQIszbdcchiUQ5dnR/ NypTgDxOnrBXTb6BfZ11LPZjTROEwFOZOJWlaFSYKGUuilT2yT0Sfr0z59dZp0gUbtCZ QoOq73Owg51N2qY5skI7ZzSuglmdVpqjEkRmapIipSVFwVt1avp3kWLZ7COpmdQUrijA OzwzSq7CBegs4TOOMsyNA2snkgMlm1E2ANXSQOi7rtjbzwXI29FalqsF/gP06nTzQLhV AByUfQee9sphwnn47OqWVhkJ55WksyoPYlmPsao4bwXJwCV/58I6yAxbms+l0eLREqCd So9g== X-Received: by 10.70.48.199 with SMTP id o7mr53433330pdn.97.1417008859802; Wed, 26 Nov 2014 05:34:19 -0800 (PST) Received: from localhost.localdomain ([165.132.120.48]) by mx.google.com with ESMTPSA id pk1sm4349746pdb.78.2014.11.26.05.34.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Nov 2014 05:34:18 -0800 (PST) From: Jungseung Lee To: "linux-arm-kernel@lists.infradead.org" , Laura Abbott , Russell King , Will Deacon , Ard Biesheuvel , Catalin Marinas , Arnd Bergmann Subject: [PATCH v3] arm: Support for the PXN CPU feature on ARMv7 Date: Wed, 26 Nov 2014 22:34:00 +0900 Message-Id: <1417008840-27591-1-git-send-email-js07.lee@gmail.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141126_053440_963924_CD4565DE X-CRM114-Status: GOOD ( 19.37 ) X-Spam-Score: -0.8 (/) Cc: Jungseung Lee X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Modern ARMv7-A/R cores optionally implement below new hardware feature: - PXN: Privileged execute-never(PXN) is a security feature. PXN bit determines whether the processor can execute software from the region. This is effective solution against ret2usr attack. On an implementation that does not include the LPAE, PXN is optionally supported. This patch set PXN bit on user page table for preventing user code execution with privilege mode. Signed-off-by: Jungseung Lee --- arch/arm/include/asm/pgalloc.h | 28 +++++++++++++++++++++++++++- arch/arm/include/asm/pgtable-2level-hwdef.h | 2 ++ arch/arm/include/asm/pgtable-3level-hwdef.h | 1 + arch/arm/mm/mmu.c | 5 +++++ 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index 78a7793..69e565e 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -17,6 +17,8 @@ #include #include #include +#include +#include #define check_pgt_cache() do { } while (0) @@ -25,6 +27,26 @@ #define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) +/* + * Once this call has completed the variable @vmsa is set to 'VMSA support' + * in case of ARMv7. + */ +static inline bool cpu_has_classic_pxn(void) +{ + if (__LINUX_ARM_ARCH__ >= 6 && !IS_ENABLED(CONFIG_ARM_LPAE)) { + static unsigned int vmsa = ~0UL; + + if (cpu_architecture() != CPU_ARCH_ARMv7) + return false; + if (vmsa == 4) + return true; + + vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0; + return vmsa == 4; + } else + return false; +} + #ifdef CONFIG_ARM_LPAE static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) @@ -157,7 +179,11 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) { - __pmd_populate(pmdp, page_to_phys(ptep), _PAGE_USER_TABLE); + pmdval_t pmdval = _PAGE_USER_TABLE; + + if (cpu_has_classic_pxn()) + pmdval |= PMD_PXNTABLE; + __pmd_populate(pmdp, page_to_phys(ptep), pmdval); } #define pmd_pgtable(pmd) pmd_page(pmd) diff --git a/arch/arm/include/asm/pgtable-2level-hwdef.h b/arch/arm/include/asm/pgtable-2level-hwdef.h index 5cfba15..5e68278 100644 --- a/arch/arm/include/asm/pgtable-2level-hwdef.h +++ b/arch/arm/include/asm/pgtable-2level-hwdef.h @@ -20,12 +20,14 @@ #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) #define PMD_TYPE_TABLE (_AT(pmdval_t, 1) << 0) #define PMD_TYPE_SECT (_AT(pmdval_t, 2) << 0) +#define PMD_PXNTABLE (_AT(pmdval_t, 1) << 2) /* v7 */ #define PMD_BIT4 (_AT(pmdval_t, 1) << 4) #define PMD_DOMAIN(x) (_AT(pmdval_t, (x)) << 5) #define PMD_PROTECTION (_AT(pmdval_t, 1) << 9) /* v5 */ /* * - section */ +#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 0) /* v7 */ #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) #define PMD_SECT_XN (_AT(pmdval_t, 1) << 4) /* v6 */ diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h index 9fd61c7..f8f1cff 100644 --- a/arch/arm/include/asm/pgtable-3level-hwdef.h +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h @@ -76,6 +76,7 @@ #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ +#define PTE_EXT_PXN (_AT(pteval_t, 1) << 53) /* PXN */ #define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ /* diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 9f98cec..5b0a047 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -605,6 +605,11 @@ static void __init build_mem_type_table(void) } kern_pgprot |= PTE_EXT_AF; vecs_pgprot |= PTE_EXT_AF; + + /* + * Set PXN for user mappings + */ + user_pgprot |= PTE_EXT_PXN; #endif for (i = 0; i < 16; i++) {