From patchwork Wed Nov 26 16:23:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5386681 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1229E9F2F5 for ; Wed, 26 Nov 2014 16:30:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 369C6201CD for ; Wed, 26 Nov 2014 16:30:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2905A201C0 for ; Wed, 26 Nov 2014 16:30:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XtfRG-0000l0-ST; Wed, 26 Nov 2014 16:27:34 +0000 Received: from mail-wi0-f173.google.com ([209.85.212.173]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XtfOD-000672-GJ for linux-arm-kernel@lists.infradead.org; Wed, 26 Nov 2014 16:24:27 +0000 Received: by mail-wi0-f173.google.com with SMTP id r20so13059310wiv.12 for ; Wed, 26 Nov 2014 08:24:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vJt6UYwtFcD+jjmhqboiOpNODP3i9QablOvYxZcCRnM=; b=j7fQftXlPnCZlDWIAKXAJcg3R7n1wEfAZ3XJCuDKhjir3MuKNDorKlCmqk0b0RZTxJ x3SbHREazt/xYfjt7L4SJ01UeT53t4PLOg1f2T7BPeuDBHXpFnRn1hL5JeibqdFusQqw 5rh4Z1uxL4nzAYCSILNXTydHfpdyLk2jZUljSeHO2G54AagAgY5yEVsEJQUResS7/ljo 7wTNRmkkdRCj/upuJKUDUfNuldcW5KczSrE1QMziSeA/JHZe8+yfqNkK9K3DKavbETjk tKQ3nYhgtEQaOmFwaV3/oWuTmBZj4CAhLaW+F0VychjHw2V2iKllhlQIg5R6Mz40G/4/ auaA== X-Gm-Message-State: ALoCoQkerdkpHI4a5M+yeX0QcXLXch+gQGMEcaNQbxEIKcSXhW1d2eCMCPBloI9JFjhlNrwlqBtA X-Received: by 10.180.11.140 with SMTP id q12mr43412550wib.45.1417019042860; Wed, 26 Nov 2014 08:24:02 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id pl6sm7869071wic.22.2014.11.26.08.24.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Nov 2014 08:24:01 -0800 (PST) From: Daniel Thompson To: Thomas Gleixner , Jason Cooper Subject: [PATCH 3.18-rc4 v10 1/6] irqchip: gic: Finer grain locking for gic_raise_softirq Date: Wed, 26 Nov 2014 16:23:25 +0000 Message-Id: <1417019010-9220-2-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1417019010-9220-1-git-send-email-daniel.thompson@linaro.org> References: <1415968543-29469-1-git-send-email-daniel.thompson@linaro.org> <1417019010-9220-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141126_082425_743999_2D952B6C X-CRM114-Status: GOOD ( 17.52 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Russell King , patches@linaro.org, Marc Zyngier , Stephen Boyd , linux-kernel@vger.kernel.org, Daniel Drake , Dmitry Pervushin , Dirk Behme , John Stultz , Tim Sander , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP irq_controller_lock is used for multiple purposes within the gic driver. Primarily it is used to make register read-modify-write sequences atomic. It is also used by gic_raise_softirq() in order that the big.LITTLE migration logic can figure out when it is safe to migrate interrupts between physical cores. The second usage of irq_controller_lock is difficult to discern when reviewing the code because the migration itself takes place outside the lock. This patch makes the second usage more explicit by splitting it out into a separate lock and providing better comments. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Russell King Cc: Marc Zyngier --- drivers/irqchip/irq-gic.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 38493ff28fa5..94d77118efa8 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -73,6 +73,12 @@ struct gic_chip_data { static DEFINE_RAW_SPINLOCK(irq_controller_lock); /* + * This lock is used by the big.LITTLE migration code to ensure no IPIs + * can be pended on the old core after the map has been updated. + */ +static DEFINE_RAW_SPINLOCK(cpu_map_migration_lock); + +/* * The GIC mapping of CPU interfaces does not necessarily match * the logical CPU numbering. Let's use a mapping as returned * by the GIC itself. @@ -624,7 +630,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) int cpu; unsigned long flags, map = 0; - raw_spin_lock_irqsave(&irq_controller_lock, flags); + raw_spin_lock_irqsave(&cpu_map_migration_lock, flags); /* Convert our logical CPU mask into a physical one. */ for_each_cpu(cpu, mask) @@ -639,7 +645,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) /* this always happens on GIC0 */ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); - raw_spin_unlock_irqrestore(&irq_controller_lock, flags); + raw_spin_unlock_irqrestore(&cpu_map_migration_lock, flags); } #endif @@ -710,8 +716,17 @@ void gic_migrate_target(unsigned int new_cpu_id) raw_spin_lock(&irq_controller_lock); - /* Update the target interface for this logical CPU */ + /* + * Update the target interface for this logical CPU + * + * From the point we release the cpu_map_migration_lock any new + * SGIs will be pended on the new cpu which makes the set of SGIs + * pending on the old cpu static. That means we can defer the + * migration until after we have released the irq_controller_lock. + */ + raw_spin_lock(&cpu_map_migration_lock); gic_cpu_map[cpu] = 1 << new_cpu_id; + raw_spin_unlock(&cpu_map_migration_lock); /* * Find all the peripheral interrupts targetting the current