| Message ID | 1417040910-43290-5-git-send-email-lina.iyer@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 11/26/2014 02:28 PM, Lina Iyer wrote: > Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to > regulate the power to the cpu and aide the core in entering idle states. > Reference the SAW instance and associate the instance with the CPU core. > > Signed-off-by: Lina Iyer <lina.iyer@linaro.org> > Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> I imagine all these dts changes will go through qcom tree -> arm-soc?
On Wed, Nov 26 2014 at 15:42 -0700, Stephen Boyd wrote: >On 11/26/2014 02:28 PM, Lina Iyer wrote: >>Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to >>regulate the power to the cpu and aide the core in entering idle states. >>Reference the SAW instance and associate the instance with the CPU core. >> >>Signed-off-by: Lina Iyer <lina.iyer@linaro.org> >> > >Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> > >I imagine all these dts changes will go through qcom tree -> arm-soc? I will ping Kumar. > >-- >Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >a Linux Foundation Collaborative Project >
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index e265ec1..5a41f44 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -21,6 +21,7 @@ reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; }; cpu@1 { @@ -30,6 +31,7 @@ reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; }; cpu@2 { @@ -39,6 +41,7 @@ reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; }; cpu@3 { @@ -48,6 +51,7 @@ reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; }; L2: l2-cache { @@ -144,7 +148,27 @@ }; }; - saw_l2: regulator@f9012000 { + saw0: power-controller@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator;
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> --- arch/arm/boot/dts/qcom-msm8974.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)