| Message ID | 1418169871-19232-2-git-send-email-rjui@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Dienstag, den 09.12.2014, 16:04 -0800 schrieb Ray Jui: > Document the PCIe device tree binding for Broadcom iProc family of SoCs > > Signed-off-by: Ray Jui <rjui@broadcom.com> > Reviewed-by: Scott Branden <sbranden@broadcom.com> > --- > .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 62 ++++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt > > diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt > new file mode 100644 > index 0000000..2467628 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt > @@ -0,0 +1,62 @@ > +* Broadcom iProc PCIe controller > + > +Required properties: > +- compatible: Must be "brcm,iproc-pcie" > +- reg: base address and length of the PCIe controller and the MDIO interface > + that controls the PCIe PHY > +- interrupts: interrupt IDs > +- bus-range: PCI bus numbers covered > +- #address-cells: set to <3> > +- #size-cells: set to <2> > +- device_type: set to "pci" > +- ranges: ranges for the PCI memory and I/O regions > +- phy-addr: MDC/MDIO adddress of the PCIe PHY > +- have-msi-inten-reg: Required for legacy iProc PCIe controllers that need the > + MSI interrupt enable register to be set explicitly > + > +The Broadcom iProc PCie driver adapts the multi-domain structure, i.e., each > +interface has its own domain and therefore has its own device node > +Example: > + > +SoC specific DT Entry: > + > + pcie0: pcie@18012000 { > + compatible = "brcm,iproc-pcie"; > + reg = <0x18012000 0x1000>, > + <0x18002000 0x1000>; > + interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, > + <GIC_SPI 97 IRQ_TYPE_NONE>, > + <GIC_SPI 98 IRQ_TYPE_NONE>, > + <GIC_SPI 99 IRQ_TYPE_NONE>, > + <GIC_SPI 100 IRQ_TYPE_NONE>, > + <GIC_SPI 101 IRQ_TYPE_NONE>; This is missing the interrupt-map and interrupt-map-mask for the legacy INTx interrupts. If you add this you don't need to have a special map function in your driver, but can just use the standard of_irq_parse_and_map_pci() function. Regards, Lucas > + bus-range = <0x00 0xFF>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x81000000 0 0 0x28000000 0 0x00010000 /* downstream I/O */ > + 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; /* non-prefetchable memory */ > + phy-addr = <5>; > + }; > + > + pcie1: pcie@18013000 { > + compatible = "brcm,iproc-pcie"; > + reg = <0x18013000 0x1000>, > + <0x18002000 0x1000>; > + > + interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>, > + <GIC_SPI 103 IRQ_TYPE_NONE>, > + <GIC_SPI 104 IRQ_TYPE_NONE>, > + <GIC_SPI 105 IRQ_TYPE_NONE>, > + <GIC_SPI 106 IRQ_TYPE_NONE>, > + <GIC_SPI 107 IRQ_TYPE_NONE>; > + bus-range = <0x00 0xFF>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x81000000 0 0 0x48000000 0 0x00010000 /* downstream I/O */ > + 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; /* non-prefetchable memory */ > + phy-addr = <6>; > + };
On 12/10/2014 2:30 AM, Lucas Stach wrote: >> +Example: >> + >> +SoC specific DT Entry: >> + >> + pcie0: pcie@18012000 { >> + compatible = "brcm,iproc-pcie"; >> + reg = <0x18012000 0x1000>, >> + <0x18002000 0x1000>; >> + interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, >> + <GIC_SPI 97 IRQ_TYPE_NONE>, >> + <GIC_SPI 98 IRQ_TYPE_NONE>, >> + <GIC_SPI 99 IRQ_TYPE_NONE>, >> + <GIC_SPI 100 IRQ_TYPE_NONE>, >> + <GIC_SPI 101 IRQ_TYPE_NONE>; > > This is missing the interrupt-map and interrupt-map-mask for the legacy > INTx interrupts. If you add this you don't need to have a special map > function in your driver, but can just use the standard > of_irq_parse_and_map_pci() function. > > Regards, > Lucas > Thanks for pointing this out. I will look into this and try it out.
diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt new file mode 100644 index 0000000..2467628 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -0,0 +1,62 @@ +* Broadcom iProc PCIe controller + +Required properties: +- compatible: Must be "brcm,iproc-pcie" +- reg: base address and length of the PCIe controller and the MDIO interface + that controls the PCIe PHY +- interrupts: interrupt IDs +- bus-range: PCI bus numbers covered +- #address-cells: set to <3> +- #size-cells: set to <2> +- device_type: set to "pci" +- ranges: ranges for the PCI memory and I/O regions +- phy-addr: MDC/MDIO adddress of the PCIe PHY +- have-msi-inten-reg: Required for legacy iProc PCIe controllers that need the + MSI interrupt enable register to be set explicitly + +The Broadcom iProc PCie driver adapts the multi-domain structure, i.e., each +interface has its own domain and therefore has its own device node +Example: + +SoC specific DT Entry: + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>, + <0x18002000 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, + <GIC_SPI 97 IRQ_TYPE_NONE>, + <GIC_SPI 98 IRQ_TYPE_NONE>, + <GIC_SPI 99 IRQ_TYPE_NONE>, + <GIC_SPI 100 IRQ_TYPE_NONE>, + <GIC_SPI 101 IRQ_TYPE_NONE>; + bus-range = <0x00 0xFF>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; /* non-prefetchable memory */ + phy-addr = <5>; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>, + <0x18002000 0x1000>; + + interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>, + <GIC_SPI 103 IRQ_TYPE_NONE>, + <GIC_SPI 104 IRQ_TYPE_NONE>, + <GIC_SPI 105 IRQ_TYPE_NONE>, + <GIC_SPI 106 IRQ_TYPE_NONE>, + <GIC_SPI 107 IRQ_TYPE_NONE>; + bus-range = <0x00 0xFF>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; /* non-prefetchable memory */ + phy-addr = <6>; + };