| Message ID | 1418831421-19370-1-git-send-email-suzuki.poulose@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Dec 17, 2014 at 03:50:21PM +0000, Suzuki K. Poulose wrote: > From: "Suzuki K. Poulose" <suzuki.poulose@arm.com> > > We initialise the SCTLR_EL1 value by read-modify-writeback > of the desired bits, leaving the other bits (including reserved > bits(RESx)) untouched. However, sometimes the boot monitor could > leave garbage values in the RESx bits which could have different > implications. This patch makes sure that all the bits, including > the RESx bits, are set to the proper state, except for the > 'endianness' control bits, EE(25) & E0E(24)- which are set early > in the el2_setup. > > Updated the state of the Bit[6] in the comment to RES0 in the > comment. > > Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > --- Looks good to me: Acked-by: Will Deacon <will.deacon@arm.com> Is this 3.19 material, or simply a cleanup/being cautious? Will
On Wed, Dec 17, 2014 at 05:39:16PM +0000, Will Deacon wrote: > On Wed, Dec 17, 2014 at 03:50:21PM +0000, Suzuki K. Poulose wrote: > > From: "Suzuki K. Poulose" <suzuki.poulose@arm.com> > > > > We initialise the SCTLR_EL1 value by read-modify-writeback > > of the desired bits, leaving the other bits (including reserved > > bits(RESx)) untouched. However, sometimes the boot monitor could > > leave garbage values in the RESx bits which could have different > > implications. This patch makes sure that all the bits, including > > the RESx bits, are set to the proper state, except for the > > 'endianness' control bits, EE(25) & E0E(24)- which are set early > > in the el2_setup. > > > > Updated the state of the Bit[6] in the comment to RES0 in the > > comment. > > > > Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> > > Cc: Will Deacon <will.deacon@arm.com> > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > --- > > Looks good to me: > > Acked-by: Will Deacon <will.deacon@arm.com> > > Is this 3.19 material, or simply a cleanup/being cautious? I'll leave this for the 3.20 merging window.
On 17/12/14 17:39, Will Deacon wrote: > On Wed, Dec 17, 2014 at 03:50:21PM +0000, Suzuki K. Poulose wrote: >> From: "Suzuki K. Poulose" <suzuki.poulose@arm.com> >> >> We initialise the SCTLR_EL1 value by read-modify-writeback >> of the desired bits, leaving the other bits (including reserved >> bits(RESx)) untouched. However, sometimes the boot monitor could >> leave garbage values in the RESx bits which could have different >> implications. This patch makes sure that all the bits, including >> the RESx bits, are set to the proper state, except for the >> 'endianness' control bits, EE(25) & E0E(24)- which are set early >> in the el2_setup. >> >> Updated the state of the Bit[6] in the comment to RES0 in the >> comment. >> >> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> >> Cc: Will Deacon <will.deacon@arm.com> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> --- > > Looks good to me: > > Acked-by: Will Deacon <will.deacon@arm.com> > > Is this 3.19 material, or simply a cleanup/being cautious? Sorry, for the late response. Yes this is kind of being cautious. Suzuki
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 4e778b1..f1bb1fc 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -244,14 +244,18 @@ ENTRY(__cpu_setup) ENDPROC(__cpu_setup) /* + * We set the desired value explicitly, including those of the + * reserved bits. The values of bits EE & E0E were set early in + * el2_setup, which are left untouched below. + * * n n T * U E WT T UD US IHBS * CE0 XWHW CZ ME TEEA S * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM - * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved - * .... .1.. .... 01.1 11.1 ..01 0001 1101 < software settings + * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved + * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings */ .type crval, #object crval: - .word 0x000802e2 // clear - .word 0x0405d11d // set + .word 0xfcffffff // clear + .word 0x34d5d91d // set