From patchwork Mon Dec 22 09:39:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5526641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DE9E99F2F7 for ; Mon, 22 Dec 2014 09:42:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 17EFA2018E for ; Mon, 22 Dec 2014 09:42:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FBFD200E6 for ; Mon, 22 Dec 2014 09:42:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y2zTS-0003OS-1H; Mon, 22 Dec 2014 09:40:22 +0000 Received: from mail-wi0-f177.google.com ([209.85.212.177]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y2zTP-0002GC-2k for linux-arm-kernel@lists.infradead.org; Mon, 22 Dec 2014 09:40:20 +0000 Received: by mail-wi0-f177.google.com with SMTP id l15so7342842wiw.10 for ; Mon, 22 Dec 2014 01:39:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q0iwnZHxNzDPB32Q3FDlWPl5rv+Jd7eb/k64jVVEfqs=; b=kKeE5em8QZacvCSg+4GNum/xJ2iBD4tYMuTvf2nqv6Qroo5R+gKMhIRmuiBO7RJDCO xtnkq6bAZKtqlcCAGyosvMr+Dn1mdp4G4EJ+LQyKIkaNxNiVqSSk/yIBF9w9oHNLHCRQ 0Oo3W5XUd4LGEshj+ixa2cLvyilyoWDRL9j4jF9upEvgYSRPZoC8a1/XZG3K8VYZ9CU/ DGnxgb6+0tHxtzgZ5qLzdIfyge4u4F1RQfPGqUn818Dxs+YG11jeUgxUFdfF+f0aXLGZ Es4OtzE9To/3szvs1VXxHFck1h031qUvgpX65W8lX94RqArYZ1DyKYPtNiFoib/LcCWQ seew== X-Gm-Message-State: ALoCoQlvZeiCO1PijZyiVmh5/l1guADbHnuTfitpatJENdmIgLh0rlIbWk9WWXmIKiceyBtjDhpn X-Received: by 10.194.241.194 with SMTP id wk2mr40133865wjc.132.1419241195229; Mon, 22 Dec 2014 01:39:55 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id gy8sm12580038wib.23.2014.12.22.01.39.52 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Dec 2014 01:39:53 -0800 (PST) From: Daniel Thompson To: Russell King , Will Deacon Subject: [PATCH 3.19-rc1 v3] arm: perf: Prevent wraparound during overflow Date: Mon, 22 Dec 2014 09:39:45 +0000 Message-Id: <1419241185-31317-1-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1416412346-8759-1-git-send-email-daniel.thompson@linaro.org> References: <1416412346-8759-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141222_014019_280026_1C42D58B X-CRM114-Status: GOOD ( 13.72 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Peter Zijlstra , patches@linaro.org, linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Ingo Molnar , Paul Mackerras , John Stultz , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the overflow threshold for a counter is set above or near the 0xffffffff boundary then the kernel may lose track of the overflow causing only events that occur *after* the overflow to be recorded. Specifically the problem occurs when the value of the performance counter overtakes its original programmed value due to wrap around. Typical solutions to this problem are either to avoid programming in values likely to be overtaken or to treat the overflow bit as the 33rd bit of the counter. Its somewhat fiddly to refactor the code to correctly handle the 33rd bit during irqsave sections (context switches for example) so instead we take the simpler approach of avoiding values likely to be overtaken. We set the limit to half of max_period because this matches the limit imposed in __hw_perf_event_init(). This causes a doubling of the interrupt rate for large threshold values, however even with a very fast counter ticking at 4GHz the interrupt rate would only be ~1Hz. Signed-off-by: Daniel Thompson Acked-by: Will Deacon --- Notes: v3: * Rebased on 3.19-rc1 and dropped the arm64 patches (which are already upstream). v2: * Remove the redundant cast to s64 (Will Deacon). arch/arm/kernel/perf_event.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 1.9.3 diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index f7c65adaa428..557e128e4df0 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -116,8 +116,14 @@ int armpmu_event_set_period(struct perf_event *event) ret = 1; } - if (left > (s64)armpmu->max_period) - left = armpmu->max_period; + /* + * Limit the maximum period to prevent the counter value + * from overtaking the one we are about to program. In + * effect we are reducing max_period to account for + * interrupt latency (and we are being very conservative). + */ + if (left > (armpmu->max_period >> 1)) + left = armpmu->max_period >> 1; local64_set(&hwc->prev_count, (u64)-left);