From patchwork Tue Dec 23 21:13:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 5535561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5371C9F1CD for ; Tue, 23 Dec 2014 21:18:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 59F4F2011D for ; Tue, 23 Dec 2014 21:18:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7CEC320108 for ; Tue, 23 Dec 2014 21:18:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y3WoN-0005e5-6d; Tue, 23 Dec 2014 21:16:11 +0000 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y3WnM-0003yJ-Mj for linux-arm-kernel@lists.infradead.org; Tue, 23 Dec 2014 21:15:10 +0000 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 12BBE844D4; Wed, 24 Dec 2014 10:14:35 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1419369275; bh=UmlYfpC3B/Jk5z+7NBc5ZcY18aqgQCDLPk7kdxXIGjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=a8xPTrjZnAov0VK2Xj2b7p2jyz9NQSyzDsalYUBk1kCOTAUI53YpHaCjXXEAgkcQm 7EawfLHlVQkgw5qBKONoyO2dt5LTRRzm5asNdJuYxZonnJ3Bz5HsLuRRoJa4a9pT5g jZJuhz1tLOudJBM8cU+K6/UY5q6fomqtsLWG9ZIs= Received: from alliedtelesyn.co.nz (Not Verified[10.32.16.32]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 3, 0, 7277) id ; Wed, 24 Dec 2014 10:14:32 +1300 Received: from MAIL/SpoolDir by alliedtelesyn.co.nz (Mercury 1.48); 24 Dec 14 10:15:09 +1300 Received: from SpoolDir by MAIL (Mercury 1.48); 24 Dec 14 10:14:41 +1300 Received: from chrisp-dl.ws.atlnz.lc (10.33.22.30) by alliedtelesyn.co.nz (Mercury 1.48) with ESMTP; 24 Dec 14 10:14:40 +1300 Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 2F76680DF8; Wed, 24 Dec 2014 10:14:00 +1300 (NZDT) From: Chris Packham To: linux-arm-kernel@lists.infradead.org Subject: [RFC/PATCHv2 3/5] clk: mvebu: armada-xp: Support for 98DX4251 Date: Wed, 24 Dec 2014 10:13:30 +1300 Message-Id: <1419369212-17047-4-git-send-email-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.2.0.rc0 In-Reply-To: <1419369212-17047-1-git-send-email-chris.packham@alliedtelesis.co.nz> References: <1419369212-17047-1-git-send-email-chris.packham@alliedtelesis.co.nz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141223_131509_066606_F9DD2C6C X-CRM114-Status: GOOD ( 13.41 ) X-Spam-Score: -0.1 (/) Cc: Andrew Lunn , Jason Cooper , Boris Brezillon , Chris Packham , Ezequiel Garcia , Gregory Clement , Maxime Ripard , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The 98DX4251 is one of a range of packet processors with integrated CPUs based on armada-xp. One difference is that the TCLK frequency is fixed at 200MHz as opposed to the fixed 250MHz used on armada-xp. Additionally the clock-gating options are a subset of what's available on the armada-xp. Signed-off-by: Chris Packham --- As per Thomas' and Andrews comments I've made this specific to the 98DX4251 and separated out the gating definitions. It should be good for other variants of what Marvell call "MSYS" but I don't have access to any to test with. v1: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/304387.html .../devicetree/bindings/clock/mvebu-core-clock.txt | 4 +++ drivers/clk/mvebu/armada-xp.c | 35 ++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt index dc5ea5b..503849e 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt @@ -34,6 +34,9 @@ The following is a list of provided IDs and clock names on Orion5x: 1 = cpuclk (CPU0 clock) 2 = ddrclk (DDR controller clock derived from CPU0 clock) +The following is a list of provided IDs and clock names on MV98DX4251: + 0 = tclk (Internal Bus clock) + Required properties: - compatible : shall be one of the following: "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks @@ -46,6 +49,7 @@ Required properties: "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC + "marvell,mv98dx4251-core-clock" - for MV98DX4251 SoC - reg : shall be the register address of the Sample-At-Reset (SAR) register - #clock-cells : from common clock binding; shall be set to 1 diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c index b309431..eb17817 100644 --- a/drivers/clk/mvebu/armada-xp.c +++ b/drivers/clk/mvebu/armada-xp.c @@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar) return 250000000; } +/* MV98DX4251 TCLK frequency is fixed to 200MHz */ +static u32 __init mv98dx4251_get_tclk_freq(void __iomem *sar) +{ + return 200000000; +} + static const u32 axp_cpu_freqs[] __initconst = { 1000000000, 1066000000, @@ -158,6 +164,14 @@ static const struct coreclk_soc_desc axp_coreclks = { .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), }; +static const struct coreclk_soc_desc mv98dx4251_coreclks = { + .get_tclk_freq = mv98dx4251_get_tclk_freq, + .get_cpu_freq = axp_get_cpu_freq, + .get_clk_ratio = axp_get_clk_ratio, + .ratios = axp_coreclk_ratios, + .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), +}; + /* * Clock Gating Control */ @@ -195,6 +209,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = { { } }; +static const struct clk_gating_soc_desc mv98dx4251_gating_desc[] __initconst = { + { "ge1", NULL, 3, 0 }, + { "ge0", NULL, 4, 0 }, + { "pex00", NULL, 5, 0 }, + { "sdio", NULL, 17, 0 }, + { "xor0", NULL, 22, 0 }, + { } +}; + static void __init axp_clk_init(struct device_node *np) { struct device_node *cgnp = @@ -206,3 +229,15 @@ static void __init axp_clk_init(struct device_node *np) mvebu_clk_gating_setup(cgnp, axp_gating_desc); } CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init); + +static void __init mv98dx4251_clk_init(struct device_node *np) +{ + struct device_node *cgnp = + of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock"); + + mvebu_coreclk_setup(np, &mv98dx4251_coreclks); + + if (cgnp) + mvebu_clk_gating_setup(cgnp, mv98dx4251_gating_desc); +} +CLK_OF_DECLARE(mv98dx4251_clk, "marvell,mv98dx4251-core-clock", mv98dx4251_clk_init);