From patchwork Tue Dec 23 21:13:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 5535531 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 741C99F39D for ; Tue, 23 Dec 2014 21:17:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5AE6320121 for ; Tue, 23 Dec 2014 21:17:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 54F0D2011D for ; Tue, 23 Dec 2014 21:17:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y3WnD-00040a-Gp; Tue, 23 Dec 2014 21:14:59 +0000 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y3Wmy-0003v8-49 for linux-arm-kernel@lists.infradead.org; Tue, 23 Dec 2014 21:14:45 +0000 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 6DF92844D1; Wed, 24 Dec 2014 10:14:23 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1419369263; bh=ldZFVTfNkMeIDhha5S/lxOw9rJz/6ySygm/9UEuzik8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=wewybBSwhQwVAlsH2i1eJyOZlLm8r05vGbmbEAWg0YEQa9hs0ZrSNTCJodBBNCHBs tSey8KedWOXqCsa1KdycXVcpRFV1MrNOXEvVmi6nEiv2jiB+i9cS41q0u40YYidAkO kSKZjKuDv9UYq1blyovq9zhaCyrODiJtouc6k31w= Received: from alliedtelesyn.co.nz (Not Verified[10.32.16.32]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 3, 0, 7277) id ; Wed, 24 Dec 2014 10:14:20 +1300 Received: from MAIL/SpoolDir by alliedtelesyn.co.nz (Mercury 1.48); 24 Dec 14 10:14:58 +1300 Received: from SpoolDir by MAIL (Mercury 1.48); 24 Dec 14 10:14:41 +1300 Received: from chrisp-dl.ws.atlnz.lc (10.33.22.30) by alliedtelesyn.co.nz (Mercury 1.48) with ESMTP; 24 Dec 14 10:14:41 +1300 Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 8163480DF8; Wed, 24 Dec 2014 10:14:01 +1300 (NZDT) From: Chris Packham To: linux-arm-kernel@lists.infradead.org Subject: [RFC/PATCHv2 4/5] ARM: mvebu: Initial support for rd-dxbc2 Date: Wed, 24 Dec 2014 10:13:31 +1300 Message-Id: <1419369212-17047-5-git-send-email-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.2.0.rc0 In-Reply-To: <1419369212-17047-1-git-send-email-chris.packham@alliedtelesis.co.nz> References: <1419369212-17047-1-git-send-email-chris.packham@alliedtelesis.co.nz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141223_131444_482119_993B6BB3 X-CRM114-Status: GOOD ( 16.20 ) X-Spam-Score: -0.1 (/) Cc: Andrew Lunn , Jason Cooper , Boris Brezillon , Chris Packham , Ezequiel Garcia , Gregory Clement , Maxime Ripard , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The 98DX4251 Control and Management subsystem is a feature reduction derivative of the ARMADA XP with some functional changes. The following table highlights differences between the ARMADA XP MV78230 and the Control and Management subsystem. There is a complete table in the "Control and Management Subsystem Functional Specification" . Feature Bobcat2 MV78230 ------- ------- ------- CPU Core (ARMv7 compliant Dual CPU @ up Dual CPU @ up with FPU) to 800 MHz to 1.6 GHz L2 Cache 2MB 1MB PCIe 1 x1 1 x4 or 4 x1 1 x1 XOR DMA 2 Channels 4 Channels SPI interface 1 Port 2 Ports Signed-off-by: Chris Packham --- I'm not sure how much of a blurb people want about the new platform. I'd just be repeating what's in Marvell's datasheets anyway. I deliberately left the copyright notice in rd-dxbc2.dts since it was created by copying armada-xp-db.dts. And I don't think anything I did is worth asserting a different copyright. At the moment the mvebu-soc-id.h definition is not strictly needed for anything but hopefully Marvell will come to the party and add the other SoCs. arch/arm/boot/dts/rd-dxbc2.dts | 109 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/mvebu-soc-id.h | 3 + 2 files changed, 112 insertions(+) create mode 100644 arch/arm/boot/dts/rd-dxbc2.dts diff --git a/arch/arm/boot/dts/rd-dxbc2.dts b/arch/arm/boot/dts/rd-dxbc2.dts new file mode 100644 index 0000000..97a72d4 --- /dev/null +++ b/arch/arm/boot/dts/rd-dxbc2.dts @@ -0,0 +1,109 @@ +/* + * Device Tree file for RD-DXBC2 board + * + * Copyright (C) 2012-2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-mv78260.dtsi" + +/ { + model = "Marvell Bobcat2 Evaluation Board"; + compatible = "marvell,axp-db", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + }; + + internal-regs { + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + + coreclk: mvebu-sar@18230 { + compatible = "marvell,mv98dx4251-core-clock"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + clock-frequency = <400000>; + status = "okay"; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; + }; + + xor@f0900 { + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.h b/arch/arm/mach-mvebu/mvebu-soc-id.h index c16bb68..98a9dca 100644 --- a/arch/arm/mach-mvebu/mvebu-soc-id.h +++ b/arch/arm/mach-mvebu/mvebu-soc-id.h @@ -24,6 +24,9 @@ #define ARMADA_375_Z1_REV 0x0 #define ARMADA_375_A0_REV 0x3 +/* Packet Processors with integrated CPU */ +#define MV98DX4251 0xFC00 + #ifdef CONFIG_ARCH_MVEBU int mvebu_get_soc_id(u32 *dev, u32 *rev); #else