From patchwork Thu Jan 8 22:52:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 5596121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9A7FCC058D for ; Thu, 8 Jan 2015 22:57:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B6A6B20561 for ; Thu, 8 Jan 2015 22:57:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C939220570 for ; Thu, 8 Jan 2015 22:57:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y9LzS-000782-I3; Thu, 08 Jan 2015 22:55:42 +0000 Received: from smtp.codeaurora.org ([198.145.11.231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y9Lz6-0005n6-UF for linux-arm-kernel@lists.infradead.org; Thu, 08 Jan 2015 22:55:22 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id E94A71412D2; Thu, 8 Jan 2015 22:55:01 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id DBB281412D9; Thu, 8 Jan 2015 22:55:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2DC241412D2; Thu, 8 Jan 2015 22:55:00 +0000 (UTC) From: Andy Gross To: linux-arm-msm@vger.kernel.org Subject: [PATCH 2/2] soc: qcom: Add device tree binding for TCSR Date: Thu, 8 Jan 2015 16:52:57 -0600 Message-Id: <1420757577-20425-3-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1420757577-20425-1-git-send-email-agross@codeaurora.org> References: <1420757577-20425-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150108_145521_198157_834BA376 X-CRM114-Status: GOOD ( 14.43 ) X-Spam-Score: -0.0 (/) Cc: devicetree@vger.kernel.org, Kumar Gala , linux-kernel@vger.kernel.org, Bjorn Andersson , Andy Gross , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree binding support for the QCOM TCSR driver. Signed-off-by: Andy Gross --- .../devicetree/bindings/soc/qcom/qcom,tcsr.txt | 33 +++++++++++++++++++ include/dt-bindings/soc/qcom,tcsr.h | 34 ++++++++++++++++++++ 2 files changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,tcsr.txt create mode 100644 include/dt-bindings/soc/qcom,tcsr.h diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr.txt new file mode 100644 index 0000000..782a307 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,tcsr.txt @@ -0,0 +1,33 @@ +QCOM TCSR (Top Control and Status Register) Driver + +The TCSR provides miscellaneous control functions and status registers for +Qualcomm processors. + +Required properties: +- compatible: must contain "qcom,tcsr" for IPQ806x and APQ8064 +- reg: Address range for TCSR registers + +Optional properties: +- qcom,usb-ctrl-select : indicates USB port type selection. Please reference + dt-bindings/soc/qcom,tcsr.h for valid USB port selection values. +- qcom,adm-a-crci-mux-sel : indicates the CRCI mux settings for peripherals. + Please reference dt-bindings/soc/qcom,tcsr.h for valid selection values. +- qcom,adm-b-crci-mux-sel : indicates the CRCI mux settings for peripherals. + Please reference dt-bindings/soc/qcom,tcsr.h for valid selection values. + +Example for IPQ8064: + +#include + + tcsr: tcsr@1a400000 { + compatible = "qcom,tcsr"; + reg = <0x1a400000 0x100>; + + qcom,usb-ctrl-select = ; + qcom,adm-a-crci-mux-sel = + < TCSR_ADM_CRCI_SEL(GSBI1, ADM_CRCI_QUP)>; + qcom,adm-b-crci-mux-sel = + < TCSR_ADM_CRCI_SEL(GSBI1, ADM_CRCI_QUP)>; + }; + + diff --git a/include/dt-bindings/soc/qcom,tcsr.h b/include/dt-bindings/soc/qcom,tcsr.h new file mode 100644 index 0000000..8e18354 --- /dev/null +++ b/include/dt-bindings/soc/qcom,tcsr.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_QCOM_TCSR_H +#define __DT_BINDINGS_QCOM_TCSR_H + +#define TCSR_USB_SELECT_USB3_P0 0x1 +#define TCSR_USB_SELECT_USB3_P1 0x2 +#define TCSR_USB_SELECT_USB3_DUAL 0x3 + +#define GSBI1 1 +#define GSBI2 2 +#define GSBI3 3 +#define GSBI4 4 +#define GSBI5 5 +#define GSBI6 6 +#define GSBI7 7 + +/* values are in pairs - RX/TX. So both are 0 or both are 1 */ +#define ADM_CRCI_QUP 0 +#define ADM_CRCI_UART 3 + +/* calculate CRCI value by shifting the value by correct shift */ +#define TCSR_ADM_CRCI_SEL(gsbi, val) (val << (gsbi-1)*2) + +#endif