@@ -61,3 +61,23 @@ DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
.init_machine = sam9g45_dt_device_init,
.dt_compat = at91_9g45_board_compat,
MACHINE_END
+
+static void __init sam9x5_dt_device_init(void)
+{
+ at91_sam9x5_pm_init();
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *at91_9x5_board_compat[] __initconst = {
+ "atmel,at91sam9x5",
+ "atmel,at91sam9n12",
+ NULL
+};
+
+DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
+ /* Maintainer: Atmel */
+ .map_io = at91_map_io,
+ .init_early = at91_dt_initialize,
+ .init_machine = sam9x5_dt_device_init,
+ .dt_compat = at91_9x5_board_compat,
+MACHINE_END
@@ -28,7 +28,7 @@
static void __init sama5_dt_device_init(void)
{
- at91_sam9260_pm_init();
+ at91_sam9x5_pm_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
@@ -306,3 +306,10 @@ void __init at91_sam9g45_pm_init(void)
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
return at91_pm_init();
}
+
+void __init at91_sam9x5_pm_init(void)
+{
+ at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
+ at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
+ return at91_pm_init();
+}
Newer SoCs: at91sam9x5, at91sam9n12, sama5d3 and sama5d4 embed a DDR controller and have a different PMC status register layout than the at91sam9g45. Create another at91_sam9x5_pm_init() function to match this compatibility. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> --- arch/arm/mach-at91/board-dt-sam9.c | 20 ++++++++++++++++++++ arch/arm/mach-at91/board-dt-sama5.c | 2 +- arch/arm/mach-at91/pm.c | 7 +++++++ 3 files changed, 28 insertions(+), 1 deletion(-)