From patchwork Fri Feb 6 13:57:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 5791911 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E7291BF440 for ; Fri, 6 Feb 2015 14:00:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 19AFC201EF for ; Fri, 6 Feb 2015 14:00:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 270EF201BC for ; Fri, 6 Feb 2015 14:00:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YJjQi-00047L-L4; Fri, 06 Feb 2015 13:58:44 +0000 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YJjQQ-0003f0-N6 for linux-arm-kernel@lists.infradead.org; Fri, 06 Feb 2015 13:58:27 +0000 Received: by mail-pa0-f47.google.com with SMTP id lj1so17422891pab.6 for ; Fri, 06 Feb 2015 05:58:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=I8angH0ET+NjowNDFUKn7hy4XUSz9wx0ofTtEZHc0tI=; b=hO0svMZY4REJ9e6ZvBeB4rDjNzcmtxA9TDmGhC3WtZbIBKHcIP8IzCGDswCzFduoOw c6WX/Gkz1j8tljAygbih41dqTEl3jTHDGxPex3109dxs3SwfM5xaUxS+XxXBX/21EeR+ Zd5K/5SUdisZrwZ2V/qxVOYZTXr42GWSGhu1lO8VBLslQ1eHqlrQe2Dr2baVTzTNnzMF fYDwWjZB5IdGY5styymtkvVwYsTmlPjK4Ly2YDlBvvZhq755d7E66zSwMjT4DJtGY6bt 1ZUVFhTBroxCVrXCe8jIxy7oNL0lJI5DiW9epdeXbfcVkz0uSGvNq8efti50cqmsoNPZ qWlA== X-Received: by 10.70.132.199 with SMTP id ow7mr5880526pdb.163.1423231085386; Fri, 06 Feb 2015 05:58:05 -0800 (PST) Received: from localhost.localdomain ([122.172.209.203]) by mx.google.com with ESMTPSA id z1sm8185652pda.78.2015.02.06.05.58.02 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Feb 2015 05:58:04 -0800 (PST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, mturquette@linaro.org Subject: [PATCH v2 3/3] clk: samsung: add cpu clock configuration data and instantiate cpu clock Date: Fri, 6 Feb 2015 19:27:46 +0530 Message-Id: <1423231066-7341-4-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1423231066-7341-1-git-send-email-a.kesavan@samsung.com> References: <1423231066-7341-1-git-send-email-a.kesavan@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150206_055826_786185_FF2F17FE X-CRM114-Status: GOOD ( 12.65 ) X-Spam-Score: -0.7 (/) Cc: kesavan.abhilash@gmail.com, linux-samsung-soc@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the Atlas CPU clock configuration data and instantiate the CPU clock type for Exynos7. Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-cpu.h | 5 +++++ drivers/clk/samsung/clk-exynos7.c | 33 ++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos7-clk.h | 3 ++- 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 24e844e..1fd7f51 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -31,6 +31,11 @@ #define E5420_KFC_DIV(kpll, pclk, aclk) \ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) +#define EXYNOS7_ATL_DIV0(aclk, pclk, atclk, pclk_dbg) \ + ((aclk << 8) | (pclk << 12) | (atclk << 20) | (pclk_dbg << 26)) +#define EXYNOS7_ATL_DIV1(pll, hpm, cntclk) \ + ((pll << 0) | (hpm << 4) | (cntclk << 8)) + /** * struct exynos_cpuclk_data: config data to setup cpu clocks. * @prate: frequency of the primary parent clock (in KHz). diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index cec026c..f2a9895 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -14,6 +14,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #include /* Register Offset definitions for CMU_TOPC (0x10570000) */ @@ -64,6 +65,30 @@ static const struct samsung_pll_rate_table pll1450x_24mhz_tbl[] = { PLL_35XX_RATE(200000000, 200, 3, 3), }; +static const struct exynos_cpuclk_cfg_data exynos7_atlclk_d[] __initconst = { + { 2100000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 5, 6), }, + { 2000000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 5, 6), }, + { 1896000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), }, + { 1800000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), }, + { 1704000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), }, + { 1600000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), }, + { 1500000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), }, + { 1400000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), }, + { 1300000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 4, 6), }, + { 1200000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), }, + { 1100000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), }, + { 1000000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), }, + { 900000, EXYNOS7_ATL_DIV0(2, 6, 6, 6), EXYNOS7_ATL_DIV1(1, 3, 6), }, + { 800000, EXYNOS7_ATL_DIV0(2, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 3, 5), }, + { 700000, EXYNOS7_ATL_DIV0(2, 5, 5, 5), EXYNOS7_ATL_DIV1(1, 3, 5), }, + { 600000, EXYNOS7_ATL_DIV0(2, 4, 4, 4), EXYNOS7_ATL_DIV1(1, 3, 4), }, + { 500000, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), }, + { 400000, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), }, + { 300000, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 2, 3), }, + { 200000, EXYNOS7_ATL_DIV0(2, 3, 3, 3), EXYNOS7_ATL_DIV1(1, 1, 3), }, + { 0 }, +}; + static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), FFACTOR(0, "ffac_topc_bus0_pll_div4", @@ -620,7 +645,13 @@ static struct samsung_cmu_info atlas_cmu_info __initdata = { static void __init exynos7_clk_atlas_init(struct device_node *np) { - samsung_cmu_register_one(np, &atlas_cmu_info); + struct samsung_clk_provider *ctx; + + ctx = samsung_cmu_register_one(np, &atlas_cmu_info); + exynos_register_cpu_clock(ctx, CLK_ATLAS_CLK, "atlclk", + mout_atlas_p[0], mout_atlas_p[1], 0, + exynos7_atlclk_d, ARRAY_SIZE(exynos7_atlclk_d), + 0, np); } CLK_OF_DECLARE(exynos7_clk_atlas, "samsung,exynos7-clock-atlas", diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 6b9465c..6df64ef 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -67,7 +67,8 @@ #define CLK_ATLAS 12 #define DOUT_SCLK_HPM_ATLAS 13 #define DOUT_ATLAS_PLL 14 -#define ATLAS_NR_CLK 15 +#define CLK_ATLAS_CLK 15 +#define ATLAS_NR_CLK 16 /* CCORE */ #define PCLK_RTC 1