From patchwork Thu Feb 12 17:46:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 5821231 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DF81D9F336 for ; Thu, 12 Feb 2015 17:54:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C14ED20172 for ; Thu, 12 Feb 2015 17:54:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B1DBD2011E for ; Thu, 12 Feb 2015 17:54:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YLxuh-0008NJ-IO; Thu, 12 Feb 2015 17:50:55 +0000 Received: from mail-wg0-x242.google.com ([2a00:1450:400c:c00::242]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YLxr3-0004bK-EH for linux-arm-kernel@lists.infradead.org; Thu, 12 Feb 2015 17:47:11 +0000 Received: by mail-wg0-f66.google.com with SMTP id l18so3544646wgh.1 for ; Thu, 12 Feb 2015 09:46:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=Dr0t/9oMldxpiMeI+PHNm6SWCylRZXru/vw0YIaOr0I=; b=Nui2Z3hloTfhC0Ti6EC2DneVguY84sRfGIu3EitXHvTuKBUvYdtTJa02BXnYA3mdX/ tU82aTqQG8BQ7uhoehJIzWKfnrvew1E1QyebBHFo0BF6IWJIQbZ/6VIfcaOX0Rk4YpAQ Jsy0qpnD9MDe2FcX6RMPO3k1w6n5Nei/El7HlakQlEXhA2+oBAblcxcm3LEbGqPOoc/l GkNJdzSNsGQZAcmYXOQ81x0W74VTg6bFU0edFvQmzkbxp+P0uufjwjh2P4IuJBaM7/G0 9JPa/0c/prXvrQnnBDZEg5da3wTbI1ZT7WlW51K18USXzZ1wA4TmLXZ1oZtqFno71QJo 1Mmw== X-Received: by 10.194.63.206 with SMTP id i14mr10000390wjs.107.1423763207852; Thu, 12 Feb 2015 09:46:47 -0800 (PST) Received: from lmecul0520.st.com. (157.162.113.78.rev.sfr.net. [78.113.162.157]) by mx.google.com with ESMTPSA id ka1sm6614924wjc.2.2015.02.12.09.46.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Feb 2015 09:46:47 -0800 (PST) From: Maxime Coquelin To: Jonathan Corbet , Maxime Coquelin , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Philipp Zabel , Russell King , Daniel Lezcano , Thomas Gleixner , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Arnd Bergmann , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org Subject: [PATCH 12/14] ARM: dts: Introduce STM32F429 MCU Date: Thu, 12 Feb 2015 18:46:02 +0100 Message-Id: <1423763164-5606-13-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1423763164-5606-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1423763164-5606-1-git-send-email-mcoquelin.stm32@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150212_094709_811789_EC886C02 X-CRM114-Status: GOOD ( 12.99 ) X-Spam-Score: -0.6 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The STMicrolectornics's STM32F419 MCU has the following main features: - Cortex-M4 core running up to @180MHz - 2MB internal flash, 256KBytes internal RAM - FMC controller to connect SDRAM, NOR and NAND memories - SD/MMC/SDIO support - Ethernet controller - USB OTFG FS & HS controllers - I2C, SPI, CAN busses support - Several 16 & 32 bits general purpose timers - Serial Audio interface - LCD controller Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32f429-disco.dts | 41 +++++ arch/arm/boot/dts/stm32f429.dtsi | 279 ++++++++++++++++++++++++++++++++++ 3 files changed, 321 insertions(+) create mode 100644 arch/arm/boot/dts/stm32f429-disco.dts create mode 100644 arch/arm/boot/dts/stm32f429.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 91bd5bd..d7da0ef 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -442,6 +442,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ stih416-b2000.dtb \ stih416-b2020.dtb \ stih416-b2020e.dtb +dtb-$(CONFIG_ARCH_STM32)+= stm32f429-disco.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts new file mode 100644 index 0000000..0e79cc1 --- /dev/null +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -0,0 +1,41 @@ +/dts-v1/; +#include "stm32f429.dtsi" + +/ { + model = "STMicroelectronics's STM32F429i-DISCO board"; + compatible = "st,stm32f429i-disco", "st,stm32f429"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/ram rdinit=/linuxrc"; + linux,stdout-path = &usart1; + }; + + memory { + reg = <0xd0000000 0x800000>; + }; + + aliases { + ttyS0 = &usart1; + }; + + soc { + usart1: usart@40011000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <2>; + label = "Front Panel LED"; + gpios = <&gpiog 14 0>; + linux,default-trigger = "heartbeat"; + }; + green { + #gpio-cells = <2>; + gpios = <&gpiog 13 0>; + default-state = "off"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi new file mode 100644 index 0000000..71293c2 --- /dev/null +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -0,0 +1,279 @@ +/* + * Device tree for STM32F429 + */ +#include "armv7-m.dtsi" +#include + +/ { + + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + clocks { + clk_sysclk: clk-sysclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_hclk: clk-hclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_pclk1: clk-pclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <45000000>; + }; + + clk_pclk2: clk-pclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + + clk_pmtr1: clk-pmtr1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + + clk_pmtr2: clk-pmtr2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_systick: clk-systick { + compatible = "fixed-factor-clock"; + clocks = <&clk_hclk>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + }; + + systick: system-timer { + clocks = <&clk_systick>; + + status = "okay"; + }; + + soc { + reset_ahb1: reset@40023810 { + #reset-cells = <1>; + compatible = "st,stm32-reset"; + reg = <0x40023810 0x4>; + }; + + reset_ahb2: reset@40023814 { + #reset-cells = <1>; + compatible = "st,stm32-reset"; + reg = <0x40023814 0x4>; + }; + + reset_ahb3: reset@40023818 { + #reset-cells = <1>; + compatible = "st,stm32-reset"; + reg = <0x40023818 0x4>; + }; + + reset_apb1: reset@40023820 { + #reset-cells = <1>; + compatible = "st,stm32-reset"; + reg = <0x40023820 0x4>; + }; + + reset_apb2: reset@40023824 { + #reset-cells = <1>; + compatible = "st,stm32-reset"; + reg = <0x40023824 0x4>; + }; + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32-pinctrl"; + ranges = <0 0x40020000 0x3000>; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + resets = <&reset_ahb1 1>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + resets = <&reset_ahb1 2>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + resets = <&reset_ahb1 3>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + resets = <&reset_ahb1 4>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + resets = <&reset_ahb1 5>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + resets = <&reset_ahb1 6>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + resets = <&reset_ahb1 7>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + resets = <&reset_ahb1 8>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + resets = <&reset_ahb1 9>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + resets = <&reset_ahb1 10>; + st,bank-name = "GPIOK"; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + st,pins { + tx = <&gpioa 9 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioa 10 ALT7 NO_PULL>; + }; + }; + }; + }; + + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + resets = <&reset_apb1 0>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + resets = <&reset_apb1 1>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + resets = <&reset_apb1 2>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&reset_apb1 3>; + clocks = <&clk_pmtr1>; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <55>; + resets = <&reset_apb1 4>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + resets = <&reset_apb1 5>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + usart1: usart@40011000 { + compatible = "st,stm32-usart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&clk_pclk2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + }; +};