From patchwork Wed Feb 25 08:39:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 5878861 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 63605BF440 for ; Wed, 25 Feb 2015 08:58:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B9EA20373 for ; Wed, 25 Feb 2015 08:58:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E7CB20304 for ; Wed, 25 Feb 2015 08:58:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YQXkw-0002Bp-Ia; Wed, 25 Feb 2015 08:55:46 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YQXZA-0000xt-LC for linux-arm-kernel@lists.infradead.org; Wed, 25 Feb 2015 08:43:37 +0000 Received: by padbj1 with SMTP id bj1so3645066pad.5 for ; Wed, 25 Feb 2015 00:43:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RcPeoc5qsyBgXbuazFFCAj0GdQwCTB129d7GEdvjRfw=; b=Yvjkiq/S+ECaBz+GfPcQL6qyrl4RRcXShzicx25GKsRmD6pZsfnqZk4sMxDz68o/kJ QScR/ynC6K3Qg5r4nZVZ6j8Kn4dOGtvh1lBSPvSEMvClJIQxq7js7uv00KQPUEWDSYDJ mCq0UzXnWw5XsL4Ts/oEJjRa8zAwd93ApD3pIgA2wl5FD3SxNp0TBgts3TFhhQyxlxG1 64gUujeo2KlsiLtD9Q6nFnocPvOvwhdPbJosW5n9tw621kFIjvXjfS5aaZuvjx0DHNRP nQTaB0Qcl4wk0sPiB63H+puyNqJ5zwvMjKUN/z5LvUF+6v3+baHZXI8gdnhcTIAk/jsG Nf4A== X-Gm-Message-State: ALoCoQnSCyrgZppXv9aNYcMOXfvsc6kAdNB4L28AKi6WG7dOj6jSrYK+mcF0C5Jvqi6t4hLNlxjd X-Received: by 10.70.91.75 with SMTP id cc11mr3691815pdb.150.1424853795197; Wed, 25 Feb 2015 00:43:15 -0800 (PST) Received: from localhost ([167.160.116.82]) by mx.google.com with ESMTPSA id t14sm16453781pbs.67.2015.02.25.00.43.11 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 25 Feb 2015 00:43:13 -0800 (PST) From: Hanjun Guo To: Catalin Marinas , "Rafael J. Wysocki" , Will Deacon , Olof Johansson , Grant Likely Subject: [PATCH v9 14/21] ACPI / processor: Make it possible to get CPU hardware ID via GICC Date: Wed, 25 Feb 2015 16:39:54 +0800 Message-Id: <1424853601-6675-15-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424853601-6675-1-git-send-email-hanjun.guo@linaro.org> References: <1424853601-6675-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150225_004336_762152_FCF86A6E X-CRM114-Status: GOOD ( 16.97 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , Ashwin Chaugule , Lorenzo Pieralisi , Robert Richter , Arnd Bergmann , Graeme Gregory , linaro-acpi@lists.linaro.org, Marc Zyngier , Jon Masters , Timur Tabi , linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, Mark Brown , Hanjun Guo , suravee.suthikulpanit@amd.com, Sudeep Holla , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained from the GICC Structure introduced by ACPI 5.1. The ARM architecture defines the MPIDR register as the CPU hardware identifier. This patch adds the code infrastructure to retrieve the MPIDR values from the ARM ACPI GICC structure in order to look-up the kernel CPU hardware ids required by the ACPI core code to identify CPUs. CC: Rafael J. Wysocki CC: Catalin Marinas CC: Will Deacon Tested-by: Suravee Suthikulpanit Tested-by: Yijing Wang Tested-by: Mark Langsdorf Tested-by: Jon Masters Tested-by: Timur Tabi Tested-by: Robert Richter Acked-by: Robert Richter Signed-off-by: Hanjun Guo Reviewed-by: Grant Likely --- arch/arm64/include/asm/acpi.h | 12 ++++++++++++ drivers/acpi/processor_core.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index 9719921..9a23369 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -13,6 +13,8 @@ #define _ASM_ACPI_H #include +#include +#include /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI @@ -27,6 +29,9 @@ static inline void __iomem *acpi_os_ioremap(acpi_physical_address phys, } #define acpi_os_ioremap acpi_os_ioremap +typedef u64 phys_cpuid_t; +#define CPU_PHYS_ID_INVALID INVALID_HWID + #define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */ extern int acpi_disabled; extern int acpi_noirq; @@ -59,6 +64,13 @@ static inline void enable_acpi(void) } /* + * The ACPI processor driver for ACPI core code needs this macro + * to find out this cpu was already mapped (mapping from CPU hardware + * ID to CPU logical ID) or not. + */ +#define cpu_physical_id(cpu) cpu_logical_map(cpu) + +/* * It's used from ACPI core in kdump to boot UP system with SMP kernel, * with this check the ACPI core will not override the CPU index * obtained from GICC with 0 and not print some error message as well. diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index a5547dc..8654adb 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -83,6 +83,31 @@ static int map_lsapic_id(struct acpi_subtable_header *entry, return 0; } +/* + * Retrieve the ARM CPU physical identifier (MPIDR) + */ +static int map_gicc_mpidr(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, phys_cpuid_t *mpidr) +{ + struct acpi_madt_generic_interrupt *gicc = + container_of(entry, struct acpi_madt_generic_interrupt, header); + + if (!(gicc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* device_declaration means Device object in DSDT, In the + * GIC interrupt model, logical processors are required to + * have a Processor Device object in the DSDT, so we should + * check device_declaration here + */ + if (device_declaration && (gicc->uid == acpi_id)) { + *mpidr = gicc->arm_mpidr; + return 0; + } + + return -EINVAL; +} + static phys_cpuid_t map_madt_entry(int type, u32 acpi_id) { unsigned long madt_end, entry; @@ -111,6 +136,9 @@ static phys_cpuid_t map_madt_entry(int type, u32 acpi_id) } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { if (!map_lsapic_id(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { + if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) + break; } entry += header->length; } @@ -143,6 +171,8 @@ static phys_cpuid_t map_mat_entry(acpi_handle handle, int type, u32 acpi_id) map_lsapic_id(header, type, acpi_id, &phys_id); else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) map_x2apic_id(header, type, acpi_id, &phys_id); + else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) + map_gicc_mpidr(header, type, acpi_id, &phys_id); exit: kfree(buffer.pointer);