From patchwork Fri Mar 6 23:41:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 5958111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 89384BF440 for ; Fri, 6 Mar 2015 23:44:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9C2C22038F for ; Fri, 6 Mar 2015 23:44:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 953392038D for ; Fri, 6 Mar 2015 23:44:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YU1ss-0002Si-0w; Fri, 06 Mar 2015 23:42:22 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YU1sm-0002Mn-53 for linux-arm-kernel@lists.infradead.org; Fri, 06 Mar 2015 23:42:17 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 0B2E41412F5; Fri, 6 Mar 2015 23:41:55 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id EFAE91412FA; Fri, 6 Mar 2015 23:41:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from sboyd-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4CA881412F5; Fri, 6 Mar 2015 23:41:54 +0000 (UTC) From: Stephen Boyd To: Mike Turquette , Stephen Boyd Subject: [PATCH v2] clk: qcom: Properly change rates for ahbix clock Date: Fri, 6 Mar 2015 15:41:53 -0800 Message-Id: <1425685313-6005-1-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 2.3.0.rc1.33.g42e4583 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150306_154216_295119_2CEBD360 X-CRM114-Status: GOOD ( 21.85 ) X-Spam-Score: -0.0 (/) Cc: linux-arm-msm@vger.kernel.org, Kenneth Westfield , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The ahbix clock can never be turned off in practice. To change the rates we need to switch the mux off the M/N counter to an always on source (XO), reprogram the M/N counter to get the rate we want and finally switch back to the M/N counter. Add a new ops structure for this type of clock so that we can set the rate properly. Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver" Cc: Kenneth Westfield Signed-off-by: Stephen Boyd Tested-by: Kenneth Westfield --- Changes from v1: * Handle the case where clock feeding M/N counter is off drivers/clk/qcom/clk-rcg.c | 62 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/lcc-ipq806x.c | 5 ++-- 3 files changed, 65 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index 0039bd7d3965..466f30ca65c2 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -495,6 +495,57 @@ static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate, return __clk_rcg_set_rate(rcg, rcg->freq_tbl); } +/* + * This type of clock has a glitch-free mux that switches between the output of + * the M/N counter and an always on clock source (XO). When clk_set_rate() is + * called we need to make sure that we don't switch to the M/N counter if it + * isn't clocking because the mux will get stuck and the clock will stop + * outputting a clock. This can happen if the framework isn't aware that this + * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix + * this we switch the mux in the enable/disable ops and reprogram the M/N + * counter in the set_rate op. We also make sure to switch away from the M/N + * counter in set_rate if software thinks the clock is off. + */ +static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + const struct freq_tbl *f; + int ret; + u32 gfm = BIT(10); + + f = qcom_find_freq(rcg->freq_tbl, rate); + if (!f) + return -EINVAL; + + /* Switch to XO to avoid glitches */ + regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); + ret = __clk_rcg_set_rate(rcg, f); + /* Switch back to M/N if it's clocking */ + if (__clk_is_enabled(hw->clk)) + regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); + + return ret; +} + +static int clk_rcg_lcc_enable(struct clk_hw *hw) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + u32 gfm = BIT(10); + + /* Use M/N */ + return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); +} + +static void clk_rcg_lcc_disable(struct clk_hw *hw) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + u32 gfm = BIT(10); + + /* Use XO */ + regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); +} + static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate) { struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); @@ -543,6 +594,17 @@ const struct clk_ops clk_rcg_bypass_ops = { }; EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops); +const struct clk_ops clk_rcg_lcc_ops = { + .enable = clk_rcg_lcc_enable, + .disable = clk_rcg_lcc_disable, + .get_parent = clk_rcg_get_parent, + .set_parent = clk_rcg_set_parent, + .recalc_rate = clk_rcg_recalc_rate, + .determine_rate = clk_rcg_determine_rate, + .set_rate = clk_rcg_lcc_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops); + const struct clk_ops clk_dyn_rcg_ops = { .enable = clk_enable_regmap, .is_enabled = clk_is_enabled_regmap, diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 687e41f91d7c..d09d06ba278e 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -96,6 +96,7 @@ struct clk_rcg { extern const struct clk_ops clk_rcg_ops; extern const struct clk_ops clk_rcg_bypass_ops; +extern const struct clk_ops clk_rcg_lcc_ops; #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c index 9e27d82c0201..a6d3a6745c4d 100644 --- a/drivers/clk/qcom/lcc-ipq806x.c +++ b/drivers/clk/qcom/lcc-ipq806x.c @@ -386,13 +386,12 @@ static struct clk_rcg ahbix_clk = { .freq_tbl = clk_tbl_ahbix, .clkr = { .enable_reg = 0x38, - .enable_mask = BIT(10), /* toggle the gfmux to select mn/pxo */ + .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "ahbix", .parent_names = lcc_pxo_pll4, .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, + .ops = &clk_rcg_lcc_ops, }, }, };