From patchwork Sat Mar 7 00:54:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 5958261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DA8C09F380 for ; Sat, 7 Mar 2015 01:03:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E3F4020392 for ; Sat, 7 Mar 2015 01:03:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 143892037E for ; Sat, 7 Mar 2015 01:03:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YU36u-0006Md-5k; Sat, 07 Mar 2015 01:00:56 +0000 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YU326-000357-2y for linux-arm-kernel@lists.infradead.org; Sat, 07 Mar 2015 00:55:59 +0000 Received: by paceu11 with SMTP id eu11so41735756pac.1 for ; Fri, 06 Mar 2015 16:55:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X9/2VIxleXIAy3UY72LSA04EsMlW5BXMCRq4cJ2dggQ=; b=cym8T2v/f7z1OD+xkgru9A4/tYbn90LrPfrnDFS0cOtvmUftUqwQH839uaqgRJgUGS hbJFC1xNe/fAORML4ftSKsWmImfCtNDltwvYRThVDH9g95i+7LeuJbKQPdcm1zL8KWvh XfSHHEyObKPDBKbFk8d0mYAxs6dXulzkyZsgr0d4IenBZ+1/a+7Wo1DlGEYHZLLaDmIO LiKmNaiJ/42pIqU85uLxd3TmjO1bdOsDOPGfGZ2kv/MdRjBP4iQtHF2SJcUm+lPL2qj+ 9fduDyNsGgs6VNR5+qZAw07SpUuDMTpnF4tZSxlS6t1SUhqF10n4DMX1XvuMkv5zq5uh GyoA== X-Received: by 10.68.211.228 with SMTP id nf4mr30580732pbc.66.1425689736979; Fri, 06 Mar 2015 16:55:36 -0800 (PST) Received: from fainelli-desktop.broadcom.com (5520-maca-inet1-outside.broadcom.com. [216.31.211.11]) by mx.google.com with ESMTPSA id kd9sm10732871pab.0.2015.03.06.16.55.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Mar 2015 16:55:35 -0800 (PST) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] ARM: B15: Add suspend/resume hooks Date: Fri, 6 Mar 2015 16:54:53 -0800 Message-Id: <1425689693-31034-6-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1425689693-31034-1-git-send-email-f.fainelli@gmail.com> References: <1425689693-31034-1-git-send-email-f.fainelli@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150306_165558_233652_8BB33770 X-CRM114-Status: GOOD ( 14.96 ) X-Spam-Score: -0.8 (/) Cc: mark.rutland@arm.com, Florian Fainelli , linux@arm.linux.org.uk, rngun@broadcom.com, arnd@arndb.de, nico@linaro.org, cernekee@gmail.com, will.deacon@arm.com, alamyliu@broadcom.com, bcm-kernel-feedback-list@broadcom.com, gregory.0xf0@gmail.com, olof@lixom.net, computersforpeace@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Broadcom Brahma-B15 CPU readahead cache registers will be restored to their Power-on-Reset values after a S3 suspend/resume cycles, so we want to restore what we had enabled before. Another thing we want to take care of is disabling the read-ahead cache prior to suspending to avoid any sort of side effect with the spinlock we need to grab to serialize register accesses. Signed-off-by: Florian Fainelli --- arch/arm/mm/cache-b15-rac.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c index 73d29741f096..adde1808c478 100644 --- a/arch/arm/mm/cache-b15-rac.c +++ b/arch/arm/mm/cache-b15-rac.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -43,6 +44,10 @@ extern void v7_flush_icache_all(void); RACENPREF_MASK << RACENDATA_SHIFT) #define RAC_ENABLED (1 << 0) +/* Special state where we want to bypass the spinlock and call directly + * into the v7 cache maintenance operations during suspend/resume + */ +#define RAC_SUSPENDED (1 << 1) static void __iomem *b15_rac_base; static DEFINE_SPINLOCK(rac_lock); @@ -98,6 +103,12 @@ void b15_flush_##name(void) \ unsigned int do_flush; \ u32 val = 0; \ \ + if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) { \ + v7_flush_##name(); \ + bar; \ + return; \ + } \ + \ spin_lock(&rac_lock); \ do_flush = test_bit(RAC_ENABLED, &b15_rac_flags); \ if (do_flush) \ @@ -233,6 +244,39 @@ static struct notifier_block b15_rac_cpu_nb = { }; #endif /* CONFIG_HOTPLUG_CPU */ +#ifdef CONFIG_PM_SLEEP +static int b15_rac_suspend(void) +{ + /* Suspend the read-ahead cache oeprations, forcing our cache + * implementation to fallback to the regular ARMv7 calls. + * + * We are guaranteed to be running on the boot CPU at this point and + * with every other CPU quiesced, so setting RAC_SUSPENDED is not racy + * here. + */ + rac_config0_reg = b15_rac_disable_and_flush(); + set_bit(RAC_SUSPENDED, &b15_rac_flags); + + return 0; +} + +static void b15_rac_resume(void) +{ + /* Coming out of a S3 suspend/resume cycle, the read-ahead cache + * register RAC_CONFIG0_REG will be restored to its default value, make + * sure we re-enable it and set the enable flag, we are also guaranteed + * to run on the boot CPU, so not racy again. + */ + __b15_rac_enable(rac_config0_reg); + clear_bit(RAC_SUSPENDED, &b15_rac_flags); +} + +static struct syscore_ops b15_rac_syscore_ops = { + .suspend = b15_rac_suspend, + .resume = b15_rac_resume, +}; +#endif + static int __init b15_rac_init(void) { struct device_node *dn; @@ -261,6 +305,10 @@ static int __init b15_rac_init(void) } #endif +#ifdef CONFIG_PM_SLEEP + register_syscore_ops(&b15_rac_syscore_ops); +#endif + spin_lock(&rac_lock); reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); for_each_possible_cpu(cpu)