From patchwork Thu Mar 12 12:15:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 5994101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 69CC2BF90F for ; Thu, 12 Mar 2015 12:40:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 91CCC203B1 for ; Thu, 12 Mar 2015 12:40:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A22EA203A1 for ; Thu, 12 Mar 2015 12:40:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YW2Mh-0004HQ-HS; Thu, 12 Mar 2015 12:37:27 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YW22v-0007yf-HI for linux-arm-kernel@lists.infradead.org; Thu, 12 Mar 2015 12:17:02 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 12 Mar 2015 05:16:09 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 12 Mar 2015 05:14:28 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 12 Mar 2015 05:14:28 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Thu, 12 Mar 2015 05:16:35 -0700 Received: from vinceh-linux.nvidia.com (Not Verified[10.19.108.63]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 12 Mar 2015 05:16:35 -0700 From: Vince Hsu To: thierry.reding@gmail.com, pdeschrijver@nvidia.com, swarren@wwwdotorg.org, gnurou@gmail.com, jroedel@suse.de, p.zabel@pengutronix.de, mturquette@linaro.org, pgaikwad@nvidia.com, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tbergstrom@nvidia.com, airlied@linux.ie, bhelgaas@google.com, tj@kernel.org, arnd@arndb.de, robh@kernel.org, will.deacon@arm.com Subject: [PATCH v2 15/17] drm/tegra: remove GR3D power sequence from driver Date: Thu, 12 Mar 2015 20:15:16 +0800 Message-ID: <1426162518-7405-16-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> References: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150312_051701_658976_13B28F6F X-CRM114-Status: GOOD ( 13.31 ) X-Spam-Score: -2.7 (--) Cc: devicetree@vger.kernel.org, Vince Hsu , linux-pm@vger.kernel.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, TVD_SUBJ_WIPE_DEBT, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We have the generic PM domain support for Tegra SoCs now. So remove the duplicated power sequence here. Signed-off-by: Vince Hsu --- drivers/gpu/drm/tegra/gr3d.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c index 0b3f2b977ba0..fd8642cdc42f 100644 --- a/drivers/gpu/drm/tegra/gr3d.c +++ b/drivers/gpu/drm/tegra/gr3d.c @@ -281,21 +281,17 @@ static int gr3d_probe(struct platform_device *pdev) } } - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk, - gr3d->rst); - if (err < 0) { - dev_err(&pdev->dev, "failed to power up 3D unit\n"); + err = clk_prepare_enable(gr3d->clk); + if (err) { + dev_err(&pdev->dev, "failed to enable clk\n"); return err; } if (gr3d->clk_secondary) { - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1, - gr3d->clk_secondary, - gr3d->rst_secondary); - if (err < 0) { - dev_err(&pdev->dev, - "failed to power up secondary 3D unit\n"); - return err; + err = clk_prepare_enable(gr3d->clk_secondary); + if (err) { + dev_err(&pdev->dev, "failed to enable secondary clk\n"); + goto err_clk_sec; } } @@ -313,7 +309,7 @@ static int gr3d_probe(struct platform_device *pdev) if (err < 0) { dev_err(&pdev->dev, "failed to register host1x client: %d\n", err); - return err; + goto err_host1x; } /* initialize address register map */ @@ -323,6 +319,13 @@ static int gr3d_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gr3d); return 0; + +err_clk_sec: + clk_disable_unprepare(gr3d->clk); +err_host1x: + clk_disable_unprepare(gr3d->clk_secondary); + + return err; } static int gr3d_remove(struct platform_device *pdev) @@ -337,12 +340,9 @@ static int gr3d_remove(struct platform_device *pdev) return err; } - if (gr3d->clk_secondary) { - tegra_powergate_power_off(TEGRA_POWERGATE_3D1); + if (gr3d->clk_secondary) clk_disable_unprepare(gr3d->clk_secondary); - } - tegra_powergate_power_off(TEGRA_POWERGATE_3D); clk_disable_unprepare(gr3d->clk); return 0;