From patchwork Thu Mar 12 12:15:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 5993881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E2DB5BF90F for ; Thu, 12 Mar 2015 12:28:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E0FCA203B1 for ; Thu, 12 Mar 2015 12:28:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC5DD2039C for ; Thu, 12 Mar 2015 12:28:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YW2Bu-0001dx-0M; Thu, 12 Mar 2015 12:26:18 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YW21n-0007I0-5L for linux-arm-kernel@lists.infradead.org; Thu, 12 Mar 2015 12:15:52 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 12 Mar 2015 05:16:07 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 12 Mar 2015 05:13:18 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 12 Mar 2015 05:13:18 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Thu, 12 Mar 2015 05:15:25 -0700 Received: from vinceh-linux.nvidia.com (Not Verified[10.19.108.63]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 12 Mar 2015 05:15:25 -0700 From: Vince Hsu To: thierry.reding@gmail.com, pdeschrijver@nvidia.com, swarren@wwwdotorg.org, gnurou@gmail.com, jroedel@suse.de, p.zabel@pengutronix.de, mturquette@linaro.org, pgaikwad@nvidia.com, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tbergstrom@nvidia.com, airlied@linux.ie, bhelgaas@google.com, tj@kernel.org, arnd@arndb.de, robh@kernel.org, will.deacon@arm.com Subject: [PATCH v2 04/17] memory: tegra: add flush operation for Tegra114 memory clients Date: Thu, 12 Mar 2015 20:15:05 +0800 Message-ID: <1426162518-7405-5-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> References: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150312_051551_293237_A6EB747C X-CRM114-Status: GOOD ( 18.50 ) X-Spam-Score: -5.0 (-----) Cc: devicetree@vger.kernel.org, Vince Hsu , linux-pm@vger.kernel.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the hot reset register table and flush related callback functions for Tegra114. Signed-off-by: Vince Hsu --- drivers/memory/tegra/mc.h | 5 ++ drivers/memory/tegra/tegra114.c | 104 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index d5d21147fc77..2c3b8db04073 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -25,6 +25,11 @@ static inline void mc_writel(struct tegra_mc *mc, u32 value, writel(value, mc->regs + offset); } +int tegra114_mc_flush(struct tegra_mc *mc, + const struct tegra_mc_hotreset *hotreset); +int tegra114_mc_flush_done(struct tegra_mc *mc, + const struct tegra_mc_hotreset *hotreset); + #ifdef CONFIG_ARCH_TEGRA_3x_SOC extern const struct tegra_mc_soc tegra30_mc_soc; #endif diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index 92ab5552fcee..b5040e653aa2 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -6,6 +6,8 @@ * published by the Free Software Foundation. */ +#include +#include #include #include @@ -914,6 +916,105 @@ static const struct tegra_smmu_swgroup tegra114_swgroups[] = { { .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, }; +static struct tegra_mc_hotreset tegra114_mc_hotreset[] = { + {TEGRA_SWGROUP_AVPC, 0x200, 0x204, 1}, + {TEGRA_SWGROUP_DC, 0x200, 0x204, 2}, + {TEGRA_SWGROUP_DCB, 0x200, 0x204, 3}, + {TEGRA_SWGROUP_EPP, 0x200, 0x204, 4}, + {TEGRA_SWGROUP_G2, 0x200, 0x204, 5}, + {TEGRA_SWGROUP_HC, 0x200, 0x204, 6}, + {TEGRA_SWGROUP_HDA, 0x200, 0x204, 7}, + {TEGRA_SWGROUP_ISP, 0x200, 0x204, 8}, + {TEGRA_SWGROUP_MPCORE, 0x200, 0x204, 9}, + {TEGRA_SWGROUP_MPCORELP, 0x200, 0x204, 10}, + {TEGRA_SWGROUP_MSENC, 0x200, 0x204, 11}, + {TEGRA_SWGROUP_NV, 0x200, 0x204, 12}, + {TEGRA_SWGROUP_PPCS, 0x200, 0x204, 14}, + {TEGRA_SWGROUP_VDE, 0x200, 0x204, 16}, + {TEGRA_SWGROUP_VI, 0x200, 0x204, 17}, +}; + +/* + * Must be called with mc->lock held + */ +static bool tegra114_stable_hotreset_check(struct tegra_mc *mc, + u32 reg, u32 *stat) +{ + int i; + u32 cur_stat; + u32 prv_stat; + + /* + * There might be a glitch seen with the status register if we program + * the control register and then read the status register in a short + * window (on the order of 5 cycles) due to a HW bug. So here we poll + * for a stable status read. + */ + prv_stat = mc_readl(mc, reg); + for (i = 0; i < 5; i++) { + cur_stat = mc_readl(mc, reg); + if (cur_stat != prv_stat) + return false; + } + *stat = cur_stat; + return true; +} + +int tegra114_mc_flush(struct tegra_mc *mc, + const struct tegra_mc_hotreset *hotreset) +{ + u32 val; + + if (!mc || !hotreset) + return -EINVAL; + + mutex_lock(&mc->lock); + + val = mc_readl(mc, hotreset->ctrl); + val |= BIT(hotreset->bit); + mc_writel(mc, val, hotreset->ctrl); + mc_readl(mc, hotreset->ctrl); + + /* poll till the flush is done */ + do { + udelay(10); + val = 0; + if (!tegra114_stable_hotreset_check(mc, hotreset->status, &val)) + continue; + } while (!(val & BIT(hotreset->bit))); + + mutex_unlock(&mc->lock); + + dev_dbg(mc->dev, "%s bit %d\n", __func__, hotreset->bit); + return 0; +} + +int tegra114_mc_flush_done(struct tegra_mc *mc, + const struct tegra_mc_hotreset *hotreset) +{ + u32 val; + + if (!mc || !hotreset) + return -EINVAL; + + mutex_lock(&mc->lock); + + val = mc_readl(mc, hotreset->ctrl); + val &= ~BIT(hotreset->bit); + mc_writel(mc, val, hotreset->ctrl); + mc_readl(mc, hotreset->ctrl); + + mutex_unlock(&mc->lock); + + dev_dbg(mc->dev, "%s bit %d\n", __func__, hotreset->bit); + return 0; +} + +static const struct tegra_mc_ops tegra114_mc_ops = { + .flush = tegra114_mc_flush, + .flush_done = tegra114_mc_flush_done, +}; + static void tegra114_flush_dcache(struct page *page, unsigned long offset, size_t size) { @@ -945,4 +1046,7 @@ const struct tegra_mc_soc tegra114_mc_soc = { .num_address_bits = 32, .atom_size = 32, .smmu = &tegra114_smmu_soc, + .hotresets = tegra114_mc_hotreset, + .num_hotresets = ARRAY_SIZE(tegra114_mc_hotreset), + .ops = &tegra114_mc_ops, };