From patchwork Thu Mar 12 21:55:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 5999811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 33D34BF90F for ; Thu, 12 Mar 2015 22:00:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4CB922011D for ; Thu, 12 Mar 2015 22:00:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DEB3200BE for ; Thu, 12 Mar 2015 22:00:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YWB74-0001GB-Lq; Thu, 12 Mar 2015 21:57:54 +0000 Received: from mail-wg0-x234.google.com ([2a00:1450:400c:c00::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YWB60-0000cF-NN for linux-arm-kernel@lists.infradead.org; Thu, 12 Mar 2015 21:56:49 +0000 Received: by wghl18 with SMTP id l18so19303115wgh.11 for ; Thu, 12 Mar 2015 14:56:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=NduXyj6TQStzr5nySQiUI0wXJqL6YwlBXGQUCnBnbOw=; b=JzYP/yb92CBsCN+hxExkwCo9ak3LplQ7HJ9Nq1ZmnaiQ+VWzGDpRnitTdN3zfl84Xn waBzGdgvckviYm9vhheZS/ahMnz1rUBUeBdgGTdkWuGM39mYUdJnwYMlr7NtyJ4to+p6 qY9lHi1kPXpXXKQwzH5PqeuzAJ5EisI3KjXzDZI4y+FSKtoQbTbIrItrlhFgqAL7afbe VWe4D8vsPZikBaAw7xP1F9tMJ3LHrRSPTaM137jEFNX+18xvR8PrCflBMSen3e8GH2z+ IT3quM91x4EHynkEp9o7FdSelv6h+ZVhMoElbs9VSGp7qNtldU7feZLA1yAWcI/IPv6l mGkg== X-Received: by 10.180.12.84 with SMTP id w20mr93378540wib.9.1426197386442; Thu, 12 Mar 2015 14:56:26 -0700 (PDT) Received: from lmecul0520.st.com. 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[88.139.208.246]) by mx.google.com with ESMTPSA id hl8sm148976wjb.38.2015.03.12.14.56.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Mar 2015 14:56:26 -0700 (PDT) From: Maxime Coquelin X-Google-Original-From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl Subject: [PATCH v3 02/15] ARM: ARMv7-M: Enlarge vector table up to 256 entries Date: Thu, 12 Mar 2015 22:55:48 +0100 Message-Id: <1426197361-19290-3-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> References: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150312_145648_952107_D877AE0D X-CRM114-Status: GOOD ( 15.87 ) X-Spam-Score: -0.6 (/) Cc: Mark Rutland , linux-doc@vger.kernel.org, Will Deacon , Nikolay Borisov , linux-api@vger.kernel.org, Jiri Slaby , Mauro Carvalho Chehab , linux-arch@vger.kernel.org, Russell King , Jonathan Corbet , Daniel Lezcano , Antti Palosaari , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, Kees Cook , Pawel Moll , Ian Campbell , Rusty Russell , Joe Perches , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Michal Marek , linux-gpio@vger.kernel.org, Greg Kroah-Hartman , linux-kernel@vger.kernel.org, mcoquelin.stm32@gmail.com, Kumar Gala , Tejun Heo , Andrew Morton , "David S. Miller" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Maxime Coquelin From Cortex-M reference manuals, the nvic supports up to 240 interrupts. So the number of entries in vectors table is up to 256. This patch adds a new config flag to specify the number of external interrupts. Some ifdeferies are added in order to respect the natural alignment without wasting too much space on smaller systems. Acked-by: Uwe Kleine-König Acked-by: Stefan Agner Signed-off-by: Maxime Coquelin --- arch/arm/kernel/entry-v7m.S | 13 +++++++++---- arch/arm/mm/Kconfig | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index 8944f49..b6c8bb9 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -117,9 +117,14 @@ ENTRY(__switch_to) ENDPROC(__switch_to) .data - .align 8 +#if CONFIG_CPU_V7M_NUM_IRQ <= 112 + .align 9 +#else + .align 10 +#endif + /* - * Vector table (64 words => 256 bytes natural alignment) + * Vector table (Natural alignment need to be ensured) */ ENTRY(vector_table) .long 0 @ 0 - Reset stack pointer @@ -138,6 +143,6 @@ ENTRY(vector_table) .long __invalid_entry @ 13 - Reserved .long __pendsv_entry @ 14 - PendSV .long __invalid_entry @ 15 - SysTick - .rept 64 - 16 - .long __irq_entry @ 16..64 - External Interrupts + .rept CONFIG_CPU_V7M_NUM_IRQ + .long __irq_entry @ External Interrupts .endr diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9b4f29e..aec53b4 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -604,6 +604,21 @@ config CPU_USE_DOMAINS This option enables or disables the use of domain switching via the set_fs() function. +config CPU_V7M_NUM_IRQ + int "Number of external interrupts connected to the NVIC" + depends on CPU_V7M + default 90 if ARCH_STM32 + default 38 if ARCH_EFM32 + default 240 + help + This option indicates the number of interrupts connected to the NVIC. + The value can be larger than the real number of interrupts supported + by the system, but must not be lower. + The default value is 240, corresponding to the maximum number of + interrupts supported by the NVIC on Cortex-M family. + + If unsure, keep default value. + # # CPU supports 36-bit I/O #