| Message ID | 1426333785-3952-5-git-send-email-jun.nie@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Saturday 14 March 2015 19:49:39 Jun Nie wrote: > Add an initial L2 Cache controller initialization. > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > This should not be needed at all, we expect all platforms to describe the l2 cache controller in DT to the degree that is required to have it probed automatically. Is there any special requirement about this platform that makes this impossible? Arnd
On Sat, Mar 14, 2015 at 10:22:39PM +0100, Arnd Bergmann wrote: > On Saturday 14 March 2015 19:49:39 Jun Nie wrote: > > Add an initial L2 Cache controller initialization. > > > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > > > > This should not be needed at all, we expect all platforms > to describe the l2 cache controller in DT to the degree > that is required to have it probed automatically. > > Is there any special requirement about this platform that > makes this impossible? The L2 device tree bindings do not cover PREFETCH_CTRL and POWER_CTRL registers. I do not remember, but there might be some reason that these registers are not defined by DT bindings, e.g. POWER_CTRL is not available on all pl310 revisions? Shawn
Hi Shawn, On Sun, 15 Mar 2015 19:48:33 -0700 Shawn Guo <shawn.guo@linaro.org> wrote: > On Sat, Mar 14, 2015 at 10:22:39PM +0100, Arnd Bergmann wrote: > > On Saturday 14 March 2015 19:49:39 Jun Nie wrote: > > > Add an initial L2 Cache controller initialization. > > > > > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > > > > > > > This should not be needed at all, we expect all platforms > > to describe the l2 cache controller in DT to the degree > > that is required to have it probed automatically. > > > > Is there any special requirement about this platform that > > makes this impossible? > > The L2 device tree bindings do not cover PREFETCH_CTRL and POWER_CTRL > registers. I do not remember, but there might be some reason that these > registers are not defined by DT bindings, e.g. POWER_CTRL is not > available on all pl310 revisions? The key may be PREFETCH_CTRL can only be accessed in Secure World. So the community require firmware/bootloader to do the setting rather than rely on linux kernel. Thanks, Jisheng
On Sat, Mar 14, 2015 at 07:49:39PM +0800, Jun Nie wrote: > +static void __init zx_l2x0_init(void) > +{ > + void __iomem *base; > + struct device_node *np; > + unsigned int val; > + > + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); > + if (!np) > + goto out; > + > + base = of_iomap(np, 0); > + if (!base) { > + of_node_put(np); > + goto out; > + } NAK, really, NAK. We're trying to get away from platforms doing crap like this. > + > + val = readl_relaxed(base + L310_PREFETCH_CTRL); > + val |= 0x70800000; > + writel_relaxed(val, base + L310_PREFETCH_CTRL); So that's: L310_PREFETCH_CTRL_DBL_LINEFILL | L310_PREFETCH_CTRL_INSTR_PREFETCH | L310_PREFETCH_CTRL_DATA_PREFETCH | L310_PREFETCH_CTRL_DBL_LINEFILL_INCR which you can enable by adding: arm,double-linefill arm,double-linefill-incr The prefetch enables are also accessible via the auxillary control register when the cache is not enabled (see below.) > + > + writel_relaxed(L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN, > + base + L310_POWER_CTRL); These should be done by your boot loader - they're highly SoC specific. > +out: > + l2x0_of_init(0x7c433C01, 0x8000c3fe); Why these random values? Firstly, the L2 code takes care of bits 0, 26, 27, 30 for you already. I fail to see why you would want to hard-code the cache size here either; the cache size is supposed to be configured by the hardware designers at implementation stage and the aux control register is supposed to take up that configuration at reset. You see to be setting bits 10-13 inclusive, which include: L310_AUX_CTRL_HIGHPRIO_SO_DEV L310_AUX_CTRL_STORE_LIMITATION L310_AUX_CTRL_EXCLUSIVE_CACHE Are you sure you're supposed to be setting these bits? Bits 28 and 29 are the same as bits 28 and 29 in the prefetch register (as in, you read or write those bits in either register and you're accessing the exact same bits.) The only possible bits you should be playing around with here which we don't have a way to cater for are bits 22, 28, 29.
diff --git a/arch/arm/mach-zx/zx296702.c b/arch/arm/mach-zx/zx296702.c index fdd7961..9c055ea 100644 --- a/arch/arm/mach-zx/zx296702.c +++ b/arch/arm/mach-zx/zx296702.c @@ -7,9 +7,52 @@ * published by the Free Software Foundation. */ +#include <linux/init.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> + +#include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "core.h" + +static void __init zx_l2x0_init(void) +{ + void __iomem *base; + struct device_node *np; + unsigned int val; + + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); + if (!np) + goto out; + + base = of_iomap(np, 0); + if (!base) { + of_node_put(np); + goto out; + } + + val = readl_relaxed(base + L310_PREFETCH_CTRL); + val |= 0x70800000; + writel_relaxed(val, base + L310_PREFETCH_CTRL); + + writel_relaxed(L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN, + base + L310_POWER_CTRL); + + iounmap(base); + of_node_put(np); + +out: + l2x0_of_init(0x7c433C01, 0x8000c3fe); +} + +static void __init zx296702_init_machine(void) +{ + zx_l2x0_init(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + static const char *zx296702_dt_compat[] __initconst = { "zte,zx296702", NULL, @@ -17,4 +60,5 @@ static const char *zx296702_dt_compat[] __initconst = { DT_MACHINE_START(ZX, "ZTE ZX296702 (Device Tree)") .dt_compat = zx296702_dt_compat, + .init_machine = zx296702_init_machine, MACHINE_END
Add an initial L2 Cache controller initialization. Signed-off-by: Jun Nie <jun.nie@linaro.org> --- arch/arm/mach-zx/zx296702.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)