From patchwork Thu Mar 19 17:19:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 6051491 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 51759BF90F for ; Thu, 19 Mar 2015 17:25:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 58D182050B for ; Thu, 19 Mar 2015 17:25:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 587DD204FC for ; Thu, 19 Mar 2015 17:25:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYe9U-0007Zd-Di; Thu, 19 Mar 2015 17:22:36 +0000 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYe6r-0004sn-V4 for linux-arm-kernel@lists.infradead.org; Thu, 19 Mar 2015 17:19:55 +0000 Received: from mirror2.csie.ntu.edu.tw (mirror2.csie.ntu.edu.tw [140.112.30.76]) (Authenticated sender: b93043) by smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id 7009A206AE; Fri, 20 Mar 2015 01:19:09 +0800 (CST) Received: by mirror2.csie.ntu.edu.tw (Postfix, from userid 1000) id 534715F76C; Fri, 20 Mar 2015 01:19:09 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Mike Turquette , Emilio Lopez Subject: [PATCH 4/6] clk: sunxi: Make divs clocks specify which output is the parent clock Date: Fri, 20 Mar 2015 01:19:06 +0800 Message-Id: <1426785548-5932-5-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426785548-5932-1-git-send-email-wens@csie.org> References: <1426785548-5932-1-git-send-email-wens@csie.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150319_101954_329341_DA834240 X-CRM114-Status: GOOD ( 17.66 ) X-Spam-Score: -2.3 (--) Cc: shuge@allwinnertech.com, Hans de Goede , Chen-Yu Tsai , kevin@allwinnertech.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current sunxi clock driver has the parent of divs clocks as the last clock output of the clock node. This makes it rather difficult to add new outputs, such as fixed dividers, which were previously unknown. This patch makes the divs clocks data structure specify which output is the parent clock, and updates all current divs clocks accordingly. We can then add new outputs after the parent clocks, at least not breaking backward compatibility with regards to the devicetree bindings. Also replace kzalloc with kcalloc in sunxi_divs_clk_setup(). Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi/clk-sunxi.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index d92e30371d8a..d28acdde364e 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -1046,13 +1046,14 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, * sunxi_divs_clk_setup() helper data */ -#define SUNXI_DIVS_MAX_QTY 2 +#define SUNXI_DIVS_MAX_QTY 4 #define SUNXI_DIVISOR_WIDTH 2 struct divs_data { const struct factors_data *factors; /* data for the factor clock */ - int ndivs; /* number of children */ + int ndivs; /* number of outputs */ struct { + u8 parent; /* is it the parent? (only one please) */ u8 fixed; /* is it a fixed divisor? if not... */ struct clk_div_table *table; /* is it a table based divisor? */ u8 shift; /* otherwise it's a normal divisor with this shift */ @@ -1075,23 +1076,26 @@ static const struct divs_data pll5_divs_data __initconst = { .div = { { .shift = 0, .pow = 0, }, /* M, DDR */ { .shift = 16, .pow = 1, }, /* P, other */ + /* No output for the parent */ } }; static const struct divs_data pll6_divs_data __initconst = { .factors = &sun4i_pll6_data, - .ndivs = 2, + .ndivs = 3, .div = { { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ { .fixed = 2 }, /* P, other */ + { .parent = 1 }, /* parent, 2x */ } }; static const struct divs_data sun6i_a31_pll6_divs_data __initconst = { .factors = &sun6i_a31_pll6_data, - .ndivs = 1, + .ndivs = 2, .div = { { .fixed = 2 }, /* normal output */ + { .parent = 1 }, /* parent, 2x */ } }; @@ -1122,6 +1126,10 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, int ndivs = SUNXI_DIVS_MAX_QTY, i = 0; int flags, clkflags; + /* if number of children known, use it */ + if (data->ndivs) + ndivs = data->ndivs; + /* Set up factor clock that we will be dividing */ pclk = sunxi_factors_clk_setup(node, data->factors); parent = __clk_get_name(pclk); @@ -1132,7 +1140,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, if (!clk_data) return; - clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); + clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL); if (!clks) goto free_clkdata; @@ -1142,15 +1150,17 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, * our RAM clock! */ clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; - /* if number of children known, use it */ - if (data->ndivs) - ndivs = data->ndivs; - for (i = 0; i < ndivs; i++) { if (of_property_read_string_index(node, "clock-output-names", i, &clk_name) != 0) break; + /* If this is the parent, just update clks and skip */ + if (data->div[i].parent) { + clk_data->clks[i] = pclk; + continue; + } + gate_hw = NULL; rate_hw = NULL; rate_ops = NULL; @@ -1209,9 +1219,6 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, clk_register_clkdev(clks[i], clk_name, NULL); } - /* The last clock available on the getter is the parent */ - clks[i++] = pclk; - /* Adjust to the real max */ clk_data->clk_num = i;