From patchwork Thu Mar 19 17:19:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 6051481 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 04AFCBF90F for ; Thu, 19 Mar 2015 17:25:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 14F062051D for ; Thu, 19 Mar 2015 17:25:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 256362050B for ; Thu, 19 Mar 2015 17:25:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYe8z-0007GD-Dz; Thu, 19 Mar 2015 17:22:05 +0000 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYe6r-0004sm-V2 for linux-arm-kernel@lists.infradead.org; Thu, 19 Mar 2015 17:19:54 +0000 Received: from mirror2.csie.ntu.edu.tw (mirror2.csie.ntu.edu.tw [140.112.30.76]) (Authenticated sender: b93043) by smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id 7905B20767; Fri, 20 Mar 2015 01:19:09 +0800 (CST) Received: by mirror2.csie.ntu.edu.tw (Postfix, from userid 1000) id 596AF5F807; Fri, 20 Mar 2015 01:19:09 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Mike Turquette , Emilio Lopez Subject: [PATCH 6/6] ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i Date: Fri, 20 Mar 2015 01:19:08 +0800 Message-Id: <1426785548-5932-7-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426785548-5932-1-git-send-email-wens@csie.org> References: <1426785548-5932-1-git-send-email-wens@csie.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150319_101954_131376_DBE61FF8 X-CRM114-Status: GOOD ( 10.32 ) X-Spam-Score: -2.3 (--) Cc: shuge@allwinnertech.com, Hans de Goede , Chen-Yu Tsai , kevin@allwinnertech.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i.dtsi | 10 ++++++++-- arch/arm/boot/dts/sun7i-a20.dtsi | 13 ++++++++++--- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index e42cbb03620f..df79b4c75b34 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -150,10 +150,16 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; + compatible = "allwinner,sun5i-a13-ahb-clk"; reg = <0x01c20054 0x4>; - clocks = <&axi>; + clocks = <&axi>, <&cpu>, <&pll6 1>; clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 1>; }; apb0: apb0@01c20054 { diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 3a8530b79f1c..52538beb969a 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -225,7 +225,8 @@ compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; + clock-output-names = "pll6_sata", "pll6_other", "pll6", + "pll6_div_4"; }; pll8: clk@01c20040 { @@ -254,10 +255,16 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; + compatible = "allwinner,sun5i-a13-ahb-clk"; reg = <0x01c20054 0x4>; - clocks = <&axi>; + clocks = <&axi>, <&pll6 3>, <&pll6 1>; clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 3>; }; ahb_gates: clk@01c20060 {