| Message ID | 1426984203-9133-8-git-send-email-stefan.wahren@i2se.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Stefan Wahren wrote: > [...] > diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi > index 98c1be6..21c1921 100644 > --- a/arch/arm/boot/dts/imx28.dtsi > +++ b/arch/arm/boot/dts/imx28.dtsi > @@ -38,12 +38,23 @@ > }; > > cpus { > - #address-cells = <0>; > + #address-cells = <1>; > #size-cells = <0>; > > - cpu { > + cpu@0 { > compatible = "arm,arm926ej-s"; > device_type = "cpu"; > + reg = <0x0>; > + operating-points = < > + /* kHz uV */ > + 261819 1350000 > + 360000 1350000 > + 392728 1450000 > + 454737 1550000 > + >; > + clocks = <&clks 4>; > + clock-latency = <61036>; /* two CLK32 periods */ > + cpu-supply = <®_vddd>; > }; > }; Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM controller runs above 196 MHz. The i.MX28 datasheet[1] lists these restrictions. VDD powers the SDRAM controller as well. From the datasheet the table "Frequency versus Voltage for EMICLK" shows: EMICLK Fmax (MHz) VDDD (V) DDR2 mDDR -------------------------------- 1.550 205.71 205.71 1.450 196.36 196.36 1.350 196.36 196.36 jbe [1] i.MX28 Applications Processors for Consumer Products Silicon Version 1.2 Document Number: IMX28CEC Rev. 3, 07/2012
Hi Juergen, > Juergen Borleis <juergen@kreuzholzen.de> hat am 24. März 2015 um 21:45 > geschrieben: > > > Stefan Wahren wrote: > > [...] > > Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM > controller runs above 196 MHz. The i.MX28 datasheet[1] lists these > restrictions. VDD powers the SDRAM controller as well. From the datasheet the > table "Frequency versus Voltage for EMICLK" shows: > > EMICLK Fmax (MHz) > VDDD (V) DDR2 mDDR > -------------------------------- > 1.550 205.71 205.71 > 1.450 196.36 196.36 > 1.350 196.36 196.36 > > jbe > > [1] > i.MX28 Applications > Processors for Consumer > Products > Silicon Version 1.2 > > Document Number: IMX28CEC > Rev. 3, 07/2012 thanks for pointing out. I will take care of it. Stefan
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index be0aee8..885c79c 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -27,12 +27,23 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; + operating-points = < + /* kHz uV */ + 261819 1350000 + 360000 1350000 + 392728 1450000 + 454737 1550000 + >; + clocks = <&clks 2>; + clock-latency = <61036>; /* two CLK32 periods */ + cpu-supply = <®_vddd>; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 98c1be6..21c1921 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -38,12 +38,23 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; + operating-points = < + /* kHz uV */ + 261819 1350000 + 360000 1350000 + 392728 1450000 + 454737 1550000 + >; + clocks = <&clks 4>; + clock-latency = <61036>; /* two CLK32 periods */ + cpu-supply = <®_vddd>; }; };
This patch adds the OPPs for i.MX23/i.MX28 which are necessary for cpufreq support. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> --- arch/arm/boot/dts/imx23.dtsi | 15 +++++++++++++-- arch/arm/boot/dts/imx28.dtsi | 15 +++++++++++++-- 2 files changed, 26 insertions(+), 4 deletions(-)