From patchwork Tue Mar 24 14:02:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 6079981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 97B5DBF90F for ; Tue, 24 Mar 2015 14:17:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 86B13201D3 for ; Tue, 24 Mar 2015 14:17:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 69116201BB for ; Tue, 24 Mar 2015 14:17:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YaPbC-0003rb-5u; Tue, 24 Mar 2015 14:14:30 +0000 Received: from mail-pd0-f179.google.com ([209.85.192.179]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YaPSV-00048D-BC for linux-arm-kernel@lists.infradead.org; Tue, 24 Mar 2015 14:05:32 +0000 Received: by pdbcz9 with SMTP id cz9so222233641pdb.3 for ; Tue, 24 Mar 2015 07:05:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1ZAD/nBLKJa31L7CuilSci3H5g8EnCWzB+FRUh/OUuA=; b=Vlr8N5RjWghyEUJG0NIPw6HI1yRICI4J8ev3f9yZh6844u1IsFb0/r2pf9ooIFxDmD wTi/54+yKBf6ItK28XzwCRCWNrAVfLDpb5hikSdZMA6qdSUAMf8jMwgCOq/qQw0Yrq0T 8tEgNgJ3n5oery6tRNMmDZ6uvqInc+NknBmdlm98rtWzN6jXcAIv9k59wDUXxsrtgBgh ygK4muH5FH+4Hl7TihhjQ/+v4GScaPBtVGmOY6qeGGQqxsMV8IsQP7YNBmzkOTnvAHRH cDNCf2j2Q60l8qXI6sIY8Qxf+9uGqQC99i1lHe8zev7zAaLzi0DdSrrIA2gKfyDNAarO 9RIQ== X-Gm-Message-State: ALoCoQn3WrISsasiAytG31XlDsdM3pfD8TlpHNJ2qlZz4XUJUPfAOYcMiFF8+nf3TdAnizq0Wi5S X-Received: by 10.66.241.36 with SMTP id wf4mr8331786pac.8.1427205909913; Tue, 24 Mar 2015 07:05:09 -0700 (PDT) Received: from localhost ([180.150.148.224]) by mx.google.com with ESMTPSA id bt2sm4381419pad.12.2015.03.24.07.05.08 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 24 Mar 2015 07:05:08 -0700 (PDT) From: Hanjun Guo To: Catalin Marinas , "Rafael J. Wysocki" , Will Deacon , Olof Johansson , Grant Likely Subject: [patch v11 14/23] ACPI / processor: Make it possible to get CPU hardware ID via GICC Date: Tue, 24 Mar 2015 22:02:47 +0800 Message-Id: <1427205776-5060-15-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427205776-5060-1-git-send-email-hanjun.guo@linaro.org> References: <1427205776-5060-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150324_070531_460129_3C6F13CF X-CRM114-Status: GOOD ( 17.11 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , Ashwin Chaugule , Lorenzo Pieralisi , Robert Richter , Arnd Bergmann , Graeme Gregory , linaro-acpi@lists.linaro.org, Marc Zyngier , Jon Masters , Timur Tabi , Mark Salter , linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, Mark Brown , Hanjun Guo , Suravee Suthikulpanit , Sudeep Holla , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained from the GICC Structure introduced by ACPI 5.1, since MPIDR for ARM64 is 64-bit, so typedef u64 for phys_cpuid_t. The ARM architecture defines the MPIDR register as the CPU hardware identifier. This patch adds the code infrastructure to retrieve the MPIDR values from the ARM ACPI GICC structure in order to look-up the kernel CPU hardware ids required by the ACPI core code to identify CPUs. CC: Rafael J. Wysocki CC: Catalin Marinas CC: Will Deacon Tested-by: Suravee Suthikulpanit Tested-by: Yijing Wang Tested-by: Mark Langsdorf Tested-by: Jon Masters Tested-by: Timur Tabi Tested-by: Robert Richter Acked-by: Robert Richter Acked-by: Lorenzo Pieralisi Acked-by: Rafael J. Wysocki Reviewed-by: Grant Likely Signed-off-by: Hanjun Guo Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/acpi.h | 12 ++++++++++++ drivers/acpi/processor_core.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index 9719921..eea0bc3 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -13,6 +13,8 @@ #define _ASM_ACPI_H #include +#include +#include /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI @@ -27,6 +29,9 @@ static inline void __iomem *acpi_os_ioremap(acpi_physical_address phys, } #define acpi_os_ioremap acpi_os_ioremap +typedef u64 phys_cpuid_t; +#define PHYS_CPUID_INVALID INVALID_HWID + #define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */ extern int acpi_disabled; extern int acpi_noirq; @@ -59,6 +64,13 @@ static inline void enable_acpi(void) } /* + * The ACPI processor driver for ACPI core code needs this macro + * to find out this cpu was already mapped (mapping from CPU hardware + * ID to CPU logical ID) or not. + */ +#define cpu_physical_id(cpu) cpu_logical_map(cpu) + +/* * It's used from ACPI core in kdump to boot UP system with SMP kernel, * with this check the ACPI core will not override the CPU index * obtained from GICC with 0 and not print some error message as well. diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 51cc299..b1ec78b 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -83,6 +83,31 @@ static int map_lsapic_id(struct acpi_subtable_header *entry, return 0; } +/* + * Retrieve the ARM CPU physical identifier (MPIDR) + */ +static int map_gicc_mpidr(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, phys_cpuid_t *mpidr) +{ + struct acpi_madt_generic_interrupt *gicc = + container_of(entry, struct acpi_madt_generic_interrupt, header); + + if (!(gicc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* device_declaration means Device object in DSDT, in the + * GIC interrupt model, logical processors are required to + * have a Processor Device object in the DSDT, so we should + * check device_declaration here + */ + if (device_declaration && (gicc->uid == acpi_id)) { + *mpidr = gicc->arm_mpidr; + return 0; + } + + return -EINVAL; +} + static phys_cpuid_t map_madt_entry(int type, u32 acpi_id) { unsigned long madt_end, entry; @@ -111,6 +136,9 @@ static phys_cpuid_t map_madt_entry(int type, u32 acpi_id) } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { if (!map_lsapic_id(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { + if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) + break; } entry += header->length; } @@ -143,6 +171,8 @@ static phys_cpuid_t map_mat_entry(acpi_handle handle, int type, u32 acpi_id) map_lsapic_id(header, type, acpi_id, &phys_id); else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) map_x2apic_id(header, type, acpi_id, &phys_id); + else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) + map_gicc_mpidr(header, type, acpi_id, &phys_id); exit: kfree(buffer.pointer);