From patchwork Tue Mar 24 17:22:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 6083971 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 669219F318 for ; Tue, 24 Mar 2015 17:27:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6DEE4201FE for ; Tue, 24 Mar 2015 17:27:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DD42201D3 for ; Tue, 24 Mar 2015 17:27:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YaSZK-0000HK-Aq; Tue, 24 Mar 2015 17:24:46 +0000 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YaSY5-00087A-P4 for linux-arm-kernel@lists.infradead.org; Tue, 24 Mar 2015 17:23:31 +0000 Received: from mirror2.csie.ntu.edu.tw (mirror2.csie.ntu.edu.tw [140.112.30.76]) (Authenticated sender: b93043) by smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id BFFD020275; Wed, 25 Mar 2015 01:23:05 +0800 (CST) Received: by mirror2.csie.ntu.edu.tw (Postfix, from userid 1000) id 914A65F70D; Wed, 25 Mar 2015 01:23:05 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Mike Turquette , Emilio Lopez Subject: [PATCH v2 1/3] clk: sunxi: Make divs clocks specify which output is the base factor clock Date: Wed, 25 Mar 2015 01:22:07 +0800 Message-Id: <1427217729-10017-2-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1427217729-10017-1-git-send-email-wens@csie.org> References: <1427217729-10017-1-git-send-email-wens@csie.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150324_102330_129603_E190AA7F X-CRM114-Status: GOOD ( 18.20 ) X-Spam-Score: -2.3 (--) Cc: shuge@allwinnertech.com, Hans de Goede , Chen-Yu Tsai , kevin@allwinnertech.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current sunxi clock driver has the base factor clock of divs clocks as the last clock output of the clock node. This makes it rather difficult to add new outputs, such as fixed dividers, which were previously unknown. This patch makes the divs clocks data structure specify which output is the factor clock, and updates all current divs clocks accordingly. We can then add new outputs after the factor clocks, at least not breaking backward compatibility with regards to the devicetree bindings. Also replace kzalloc with kcalloc in sunxi_divs_clk_setup(). Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi/clk-sunxi.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index d92e30371d8a..9f31314a9cd7 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -1046,13 +1046,20 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, * sunxi_divs_clk_setup() helper data */ -#define SUNXI_DIVS_MAX_QTY 2 +#define SUNXI_DIVS_MAX_QTY 4 #define SUNXI_DIVISOR_WIDTH 2 struct divs_data { const struct factors_data *factors; /* data for the factor clock */ - int ndivs; /* number of children */ + int ndivs; /* number of outputs */ + /* + * List of outputs. Refer to the diagram for sunxi_divs_clk_setup(): + * self or base factor clock refers to the output from the pll + * itself. The remaining refer to fixed or configurable divider + * outputs. + */ struct { + u8 self; /* is it the base factor clock? (only one) */ u8 fixed; /* is it a fixed divisor? if not... */ struct clk_div_table *table; /* is it a table based divisor? */ u8 shift; /* otherwise it's a normal divisor with this shift */ @@ -1075,23 +1082,26 @@ static const struct divs_data pll5_divs_data __initconst = { .div = { { .shift = 0, .pow = 0, }, /* M, DDR */ { .shift = 16, .pow = 1, }, /* P, other */ + /* No output for the base factor clock */ } }; static const struct divs_data pll6_divs_data __initconst = { .factors = &sun4i_pll6_data, - .ndivs = 2, + .ndivs = 3, .div = { { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ { .fixed = 2 }, /* P, other */ + { .self = 1 }, /* base factor clock, 2x */ } }; static const struct divs_data sun6i_a31_pll6_divs_data __initconst = { .factors = &sun6i_a31_pll6_data, - .ndivs = 1, + .ndivs = 2, .div = { { .fixed = 2 }, /* normal output */ + { .self = 1 }, /* base factor clock, 2x */ } }; @@ -1122,6 +1132,10 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, int ndivs = SUNXI_DIVS_MAX_QTY, i = 0; int flags, clkflags; + /* if number of children known, use it */ + if (data->ndivs) + ndivs = data->ndivs; + /* Set up factor clock that we will be dividing */ pclk = sunxi_factors_clk_setup(node, data->factors); parent = __clk_get_name(pclk); @@ -1132,7 +1146,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, if (!clk_data) return; - clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); + clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL); if (!clks) goto free_clkdata; @@ -1142,15 +1156,17 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, * our RAM clock! */ clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; - /* if number of children known, use it */ - if (data->ndivs) - ndivs = data->ndivs; - for (i = 0; i < ndivs; i++) { if (of_property_read_string_index(node, "clock-output-names", i, &clk_name) != 0) break; + /* If this is the base factor clock, only update clks */ + if (data->div[i].self) { + clk_data->clks[i] = pclk; + continue; + } + gate_hw = NULL; rate_hw = NULL; rate_ops = NULL; @@ -1209,9 +1225,6 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, clk_register_clkdev(clks[i], clk_name, NULL); } - /* The last clock available on the getter is the parent */ - clks[i++] = pclk; - /* Adjust to the real max */ clk_data->clk_num = i;