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Tue, 24 Mar 2015 23:41:16 -0700 From: Minghuan Lian To: Subject: [PATCH 3/3] pci/layerscape: Add LS2085A PCIe support Date: Wed, 25 Mar 2015 14:42:41 +0800 Message-ID: <1427265761-31828-4-git-send-email-Minghuan.Lian@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427265761-31828-1-git-send-email-Minghuan.Lian@freescale.com> References: <1427265761-31828-1-git-send-email-Minghuan.Lian@freescale.com> X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Minghuan.Lian@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(77096005)(47776003)(2950100001)(110136001)(229853001)(77156002)(62966003)(92566002)(87936001)(86362001)(46102003)(85426001)(106466001)(50986999)(76176999)(105606002)(19580405001)(19580395003)(2351001)(50226001)(36756003)(50466002)(48376002); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB568; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB568; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:BLUPR03MB568; BCL:0; PCL:0; RULEID:; SRVR:BLUPR03MB568; X-Forefront-PRVS: 052670E5A4 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2015 06:41:21.3283 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB568 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150324_234126_639314_1170C1EF X-CRM114-Status: GOOD ( 19.84 ) X-Spam-Score: -0.0 (/) Cc: Arnd Bergmann , Minghuan Lian , Jingoo Han , Hu Mingkai-B21284 , Zang Roy-R61911 , Yoder Stuart-B08248 , Bjorn Helgaas , Scott Wood , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP LS2085a is based on arm64 architecture, however, currently, layerscape PCIe driver based on pci-desginware.c is not compatible with arm64 architecture. The patch changes code to reuse PCIe Designware Base driver and provides LS2085a PCIe support. Signed-off-by: Minghuan Lian --- drivers/pci/host/Kconfig | 4 +- drivers/pci/host/pci-layerscape.c | 188 +++++++++++++++++++------------- drivers/pci/host/pcie-designware-base.h | 3 + 3 files changed, 115 insertions(+), 80 deletions(-) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index f883d47..796e58f 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -99,8 +99,8 @@ config PCI_XGENE config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" - depends on OF && ARM - select PCIE_DW + depends on OF && (ARM || ARM64) + select PCIE_DW_BASE select MFD_SYSCON help Say Y here if you want PCIe controller support on Layerscape SoCs. diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 68c9e5e..ca64f6a 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -1,7 +1,7 @@ /* * PCIe host controller driver for Freescale Layerscape SoCs * - * Copyright (C) 2014 Freescale Semiconductor. + * Copyright (C) 2014 - 2015 Freescale Semiconductor. * * Author: Minghuan Lian * @@ -11,20 +11,16 @@ */ #include -#include -#include +#include #include #include #include -#include -#include #include #include -#include -#include #include +#include -#include "pcie-designware.h" +#include "pcie-designware-base.h" /* PEX1/2 Misc Ports Status Register */ #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) @@ -32,26 +28,29 @@ #define LTSSM_STATE_MASK 0x3f #define LTSSM_PCIE_L0 0x11 /* L0 state */ -/* Symbol Timer Register and Filter Mask Register 1 */ -#define PCIE_STRFMR1 0x71c +/* PEX LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug register */ + +#define PCIE_ATU_NUM 6 struct ls_pcie { - struct list_head node; - struct device *dev; - struct pci_bus *bus; - void __iomem *dbi; - struct regmap *scfg; - struct pcie_port pp; - int index; - int msi_irq; + struct dw_pcie_port pp; + void __iomem *regs; + void __iomem *lut; + struct regmap *scfg; + int index; }; #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) -static int ls_pcie_link_up(struct pcie_port *pp) +static int ls1_pcie_link_up(struct dw_pcie_port *pp) { - u32 state; struct ls_pcie *pcie = to_ls_pcie(pp); + u32 state; + + if (!pcie->scfg) + return 0; regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; @@ -62,94 +61,133 @@ static int ls_pcie_link_up(struct pcie_port *pp) return 1; } -static void ls_pcie_host_init(struct pcie_port *pp) +static int ls1_pcie_host_init(struct dw_pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); - int count = 0; - u32 val; - - dw_pcie_setup_rc(pp); + u32 val, index[2]; + int ret; - while (!ls_pcie_link_up(pp)) { - usleep_range(100, 1000); - count++; - if (count >= 200) { - dev_err(pp->dev, "phy link never came up\n"); - return; - } + pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, + "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(pp->dev, "No syscfg phandle specified\n"); + return PTR_ERR(pcie->scfg); } + ret = of_property_read_u32_array(pp->dev->of_node, + "fsl,pcie-scfg", index, 2); + if (ret) + return ret; + + pcie->index = index[1]; + /* * LS1021A Workaround for internal TKT228622 * to fix the INTx hang issue */ - val = ioread32(pcie->dbi + PCIE_STRFMR1); + val = dw_pcie_dbi_read(pp, PCIE_SYMBOL_TIMER_1); val &= 0xffff; - iowrite32(val, pcie->dbi + PCIE_STRFMR1); + dw_pcie_dbi_write(pp, val, PCIE_SYMBOL_TIMER_1); + + /* Fix class value */ + val = dw_pcie_dbi_read(pp, PCI_CLASS_REVISION); + val = (val & 0x0000ffff) | (PCI_CLASS_BRIDGE_PCI << 16); + dw_pcie_dbi_write(pp, val, PCI_CLASS_REVISION); + + if (!ls1_pcie_link_up(pp)) + dev_err(pp->dev, "phy link never came up\n"); + + return 0; } -static struct pcie_host_ops ls_pcie_host_ops = { - .link_up = ls_pcie_link_up, - .host_init = ls_pcie_host_init, +static struct dw_host_ops ls1_dw_host_ops = { + .link_up = ls1_pcie_link_up, + .host_init = ls1_pcie_host_init, }; -static int ls_add_pcie_port(struct ls_pcie *pcie) +static int ls2_pcie_link_up(struct dw_pcie_port *pp) { - struct pcie_port *pp; - int ret; + struct ls_pcie *pcie = to_ls_pcie(pp); + u32 state; - pp = &pcie->pp; - pp->dev = pcie->dev; - pp->dbi_base = pcie->dbi; - pp->root_bus_nr = -1; - pp->ops = &ls_pcie_host_ops; + if (!pcie->lut) + return 0; - ret = dw_pcie_host_init(pp); - if (ret) { - dev_err(pp->dev, "failed to initialize host\n"); - return ret; - } + state = ioread32(pcie->lut + PCIE_LUT_DBG) & LTSSM_STATE_MASK; + if (state < LTSSM_PCIE_L0) + return 0; + + return 1; +} + +static int ls2_pcie_host_init(struct dw_pcie_port *pp) +{ + struct ls_pcie *pcie = to_ls_pcie(pp); + u32 val; + + pcie->lut = pp->dbi + PCIE_LUT_BASE; + + dw_pcie_dbi_write(pp, 1, PCIE_DBI_RO_WR_EN); + /* Fix class value */ + val = dw_pcie_dbi_read(pp, PCI_CLASS_REVISION); + val = (val & 0x0000ffff) | (PCI_CLASS_BRIDGE_PCI << 16); + dw_pcie_dbi_write(pp, val, PCI_CLASS_REVISION); + /* clean multi-func bit */ + val = dw_pcie_dbi_read(pp, PCI_HEADER_TYPE & ~0x3); + val &= ~(1 << 23); + dw_pcie_dbi_write(pp, val, PCI_HEADER_TYPE & ~0x3); + dw_pcie_dbi_write(pp, 0, PCIE_DBI_RO_WR_EN); + + if (!ls2_pcie_link_up(pp)) + dev_err(pp->dev, "phy link never came up\n"); return 0; } +static struct dw_host_ops ls2_dw_host_ops = { + .link_up = ls2_pcie_link_up, + .host_init = ls2_pcie_host_init, +}; + +static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1021a-pcie", .data = &ls1_dw_host_ops }, + { .compatible = "fsl,ls2085a-pcie", .data = &ls2_dw_host_ops }, + { }, +}; +MODULE_DEVICE_TABLE(of, ls_pcie_of_match); + static int __init ls_pcie_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct ls_pcie *pcie; - struct resource *dbi_base; - u32 index[2]; + struct resource *res; int ret; + match = of_match_device(ls_pcie_of_match, &pdev->dev); + if (!match) + return -ENODEV; + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; - pcie->dev = &pdev->dev; - - dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); - if (!dbi_base) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); + if (!res) { dev_err(&pdev->dev, "missing *regs* space\n"); return -ENODEV; } - pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); - if (IS_ERR(pcie->dbi)) - return PTR_ERR(pcie->dbi); - - pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "fsl,pcie-scfg"); - if (IS_ERR(pcie->scfg)) { - dev_err(&pdev->dev, "No syscfg phandle specified\n"); - return PTR_ERR(pcie->scfg); - } + pcie->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pcie->regs)) + return PTR_ERR(pcie->regs); - ret = of_property_read_u32_array(pdev->dev.of_node, - "fsl,pcie-scfg", index, 2); - if (ret) - return ret; - pcie->index = index[1]; + pcie->lut = pcie->regs + PCIE_LUT_BASE; + pcie->pp.dev = &pdev->dev; + pcie->pp.dbi = pcie->regs; + pcie->pp.dw_ops = (struct dw_host_ops *)match->data; + pcie->pp.atu_num = PCIE_ATU_NUM; - ret = ls_add_pcie_port(pcie); + ret = dw_pcie_port_init(&pcie->pp); if (ret < 0) return ret; @@ -158,12 +196,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id ls_pcie_of_match[] = { - { .compatible = "fsl,ls1021a-pcie" }, - { }, -}; -MODULE_DEVICE_TABLE(of, ls_pcie_of_match); - static struct platform_driver ls_pcie_driver = { .driver = { .name = "layerscape-pcie", diff --git a/drivers/pci/host/pcie-designware-base.h b/drivers/pci/host/pcie-designware-base.h index dd7a3b3..84d65d1 100644 --- a/drivers/pci/host/pcie-designware-base.h +++ b/drivers/pci/host/pcie-designware-base.h @@ -10,6 +10,9 @@ #define _PCIE_DESIGNWARE_BASE_H /* Synopsis specific PCIE configuration registers */ +#define PCIE_SYMBOL_TIMER_1 0x71c +#define PCIE_DBI_RO_WR_EN 0x8bc + #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)