From patchwork Wed Apr 1 21:20:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joachim Eastwood X-Patchwork-Id: 6142411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E6F559F2EC for ; Wed, 1 Apr 2015 21:27:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EC57A202F0 for ; Wed, 1 Apr 2015 21:27:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 035B2202EC for ; Wed, 1 Apr 2015 21:27:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YdQ7V-0003VN-L9; Wed, 01 Apr 2015 21:24:17 +0000 Received: from mail-la0-x22f.google.com ([2a00:1450:4010:c03::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YdQ4f-0001kW-4A for linux-arm-kernel@lists.infradead.org; Wed, 01 Apr 2015 21:21:22 +0000 Received: by lahf3 with SMTP id f3so46004630lah.2 for ; Wed, 01 Apr 2015 14:20:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a6md8GGIzRRxQ00GwzEYyDiHEChZsy0k310vusKHNdc=; b=V/WzgQ1V5mUCyRuJCf0Tcdltnpey6vKjc8/7duzixc/aJmCaSIQe2OxnYA9M3ZEfHy fOrQytBMnJqZWl7Ou6wZB7NLAtRygEqRsIAlDgHCTC0RdL1/JImksWO65zLw7kIcePFB pj2cOazyhyl5tFYbImuYUklKE/97r9vjQyRM32LaslJEYnc+eqE1oB29czKqrU/pVkCL viJpx7TWfrh8TafGuVca5BCRVh9AShCfblqO5H9TewDqUqHC6oVKTH59+iP3YZeWSaVd HfHCv+4M4f55F5KmPx+WLSBKhFTGzgpUMeNrRM2wYHcC6VF+C6nucLn3ApvLo/4W4Bp6 BbKw== X-Received: by 10.113.4.105 with SMTP id cd9mr36406562lbd.38.1427923258630; Wed, 01 Apr 2015 14:20:58 -0700 (PDT) Received: from localhost.localdomain (183.90-149-48.nextgentel.com. [90.149.48.183]) by mx.google.com with ESMTPSA id ba3sm645219lbc.35.2015.04.01.14.20.55 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 01 Apr 2015 14:20:58 -0700 (PDT) From: Joachim Eastwood To: daniel.lezcano@linaro.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: dts: Add base DT for NXP LPC18xx and LPC4357 Date: Wed, 1 Apr 2015 23:20:41 +0200 Message-Id: <1427923243-26296-5-git-send-email-manabian@gmail.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1427923243-26296-1-git-send-email-manabian@gmail.com> References: <1427923243-26296-1-git-send-email-manabian@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150401_142121_402153_F57F8039 X-CRM114-Status: GOOD ( 11.35 ) X-Spam-Score: -0.8 (/) Cc: Joachim Eastwood , ariel.dalessandro@gmail.com, ezequiel@vanguardiasur.com.ar, u.kleine-koenig@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP NXP LPC18xx/43xx SoCs are very similar devices and should be able to share a common base (lpc18xx.dtsi). Diffences between the devices are put in a dtsi which is specific to that device. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 117 +++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/lpc4357.dtsi | 39 ++++++++++++++ 2 files changed, 156 insertions(+) create mode 100644 arch/arm/boot/dts/lpc18xx.dtsi create mode 100644 arch/arm/boot/dts/lpc4357.dtsi diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi new file mode 100644 index 000000000000..161e98b442e0 --- /dev/null +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -0,0 +1,117 @@ +/* + * Common base for NXP LPC18xx and LPC43xx devices. + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +#include "armv7-m.dtsi" + +/ { + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m3"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + clocks { + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + /* Temporary hardcode PLL1 until clk drivers are merged */ + pll1: pll1 { + compatible = "fixed-factor-clock"; + clocks = <&xtal>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <12>; + }; + }; + + soc { + uart0: serial@40081000 { + compatible = "ns16550a"; + reg = <0x40081000 0x1000>; + reg-shift = <2>; + interrupts = <24>; + clocks = <&pll1>; + status = "disabled"; + }; + + uart1: serial@40082000 { + compatible = "ns16550a"; + reg = <0x40082000 0x1000>; + reg-shift = <2>; + interrupts = <25>; + clocks = <&pll1>; + status = "disabled"; + }; + + timer0: timer@40084000 { + compatible = "nxp,lpc3250-timer"; + reg = <0x40084000 0x1000>; + interrupts = <12>; + clocks = <&pll1>; + }; + + timer1: timer@40085000 { + compatible = "nxp,lpc3250-timer"; + reg = <0x40085000 0x1000>; + interrupts = <13>; + clocks = <&pll1>; + }; + + uart2: serial@400c1000 { + compatible = "ns16550a"; + reg = <0x400c1000 0x1000>; + reg-shift = <2>; + interrupts = <26>; + clocks = <&pll1>; + status = "disabled"; + }; + + uart3: serial@400c2000 { + compatible = "ns16550a"; + reg = <0x400c2000 0x1000>; + reg-shift = <2>; + interrupts = <27>; + clocks = <&pll1>; + status = "disabled"; + }; + + timer2: timer@400c3000 { + compatible = "nxp,lpc3250-timer"; + reg = <0x400c3000 0x1000>; + interrupts = <14>; + clocks = <&pll1>; + }; + + timer3: timer@400c4000 { + compatible = "nxp,lpc3250-timer"; + reg = <0x400c4000 0x1000>; + interrupts = <15>; + clocks = <&pll1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/lpc4357.dtsi b/arch/arm/boot/dts/lpc4357.dtsi new file mode 100644 index 000000000000..9a3ec7663419 --- /dev/null +++ b/arch/arm/boot/dts/lpc4357.dtsi @@ -0,0 +1,39 @@ +/* + * NXP LPC4357 SoC + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/ { + compatible = "nxp,lpc4357"; + + cpus { + cpu@0 { + compatible = "arm,cortex-m4"; + }; + }; + + soc { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ + }; + + sram1: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ + }; + + sram2: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + }; + }; +};