From patchwork Fri Apr 10 09:51:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 6194181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CAB579F1C4 for ; Fri, 10 Apr 2015 09:55:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 79C8E203C0 for ; Fri, 10 Apr 2015 09:55:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 24497203A0 for ; Fri, 10 Apr 2015 09:55:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YgVct-0005GU-69; Fri, 10 Apr 2015 09:53:27 +0000 Received: from mail-wi0-f170.google.com ([209.85.212.170]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YgVc6-0004ki-EF for linux-arm-kernel@lists.infradead.org; Fri, 10 Apr 2015 09:52:40 +0000 Received: by widdi4 with SMTP id di4so121977172wid.0 for ; Fri, 10 Apr 2015 02:52:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aP8AGh0gSEhw6ncqiZXluvBMl1HyJX0vbbuE1nMpWC8=; b=AKucxSKF3w3dsb3Ae45ZtVWQWkK2ntxAF+O2Lse63xpNZTnCb1H6P4dIA7sqkZQ+So Dw/WtJTWTU36o3Z13vaEF4ndH1eGIKNzKPpFVFZTkw1UqG3BCKSUwCes8rgipcsPK2pX nH6vUM52YEsM/RCcM168uBwQ4pJyAKRWkUKrjQSFvBqAFWaK8XTaLrIkm4dHnty4Sr1p WhdY/OTcAMLoWm7la12kIGGu4GRmpujsSko+rb9nMzZ6/jqIIXO/mmxjcwYvRBxPyub8 utortn1+CMGrzZ/HcHYbgGZ+nYZ591pnxUYToTTmxIzdzXgnGolfn4LFPAoZbX1MHghg q9nA== X-Gm-Message-State: ALoCoQkSE0+WhuDcoArvXbJTPXvs7ptK0YHBHmtnNvgGAjZ+eb/9M7FuNjwFJapO6CbVvii+rSjg X-Received: by 10.194.62.52 with SMTP id v20mr1414008wjr.137.1428659536814; Fri, 10 Apr 2015 02:52:16 -0700 (PDT) Received: from wychelm.lan (cpc4-aztw19-0-0-cust71.18-1.cable.virginm.net. [82.33.25.72]) by mx.google.com with ESMTPSA id ge8sm2136126wjc.32.2015.04.10.02.52.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Apr 2015 02:52:15 -0700 (PDT) From: Daniel Thompson To: Thomas Gleixner , Jason Cooper Subject: [RESEND PATCH 4.0-rc7 v20 2/6] irqchip: gic: Make gic_raise_softirq FIQ-safe Date: Fri, 10 Apr 2015 10:51:47 +0100 Message-Id: <1428659511-9590-3-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1428659511-9590-1-git-send-email-daniel.thompson@linaro.org> References: <1427216014-5324-1-git-send-email-daniel.thompson@linaro.org> <1428659511-9590-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150410_025238_844016_88A66EE8 X-CRM114-Status: GOOD ( 16.79 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Russell King , patches@linaro.org, Marc Zyngier , Stephen Boyd , Will Deacon , linux-kernel@vger.kernel.org, Steven Rostedt , Daniel Drake , Dmitry Pervushin , Dirk Behme , John Stultz , Tim Sander , Catalin Marinas , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It is currently possible for FIQ handlers to re-enter gic_raise_softirq() and lock up. gic_raise_softirq() lock(x); -~-> FIQ handle_fiq() gic_raise_softirq() lock(x); <-- Lockup arch/arm/ uses IPIs to implement arch_irq_work_raise(), thus this issue renders it difficult for FIQ handlers to safely defer work to less restrictive calling contexts. This patch fixes the problem by converting the cpu_map_migration_lock into a rwlock making it safe to re-enter the function. Note that having made it safe to re-enter gic_raise_softirq() we no longer need to mask interrupts during gic_raise_softirq() because the b.L migration is always performed from task context. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Russell King Cc: Marc Zyngier Acked-by: Nicolas Pitre Acked-by: Marc Zyngier --- drivers/irqchip/irq-gic.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index a181b836d5ea..578ffc5ec087 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -75,22 +75,25 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock); /* * This lock is used by the big.LITTLE migration code to ensure no IPIs * can be pended on the old core after the map has been updated. + * + * This lock may be locked for reading from both IRQ and FIQ handlers + * and therefore must not be locked for writing when these are enabled. */ #ifdef CONFIG_BL_SWITCHER -static DEFINE_RAW_SPINLOCK(cpu_map_migration_lock); +static DEFINE_RWLOCK(cpu_map_migration_lock); -static inline void gic_migration_lock(unsigned long *flags) +static inline void gic_migration_lock(void) { - raw_spin_lock_irqsave(&cpu_map_migration_lock, *flags); + read_lock(&cpu_map_migration_lock); } -static inline void gic_migration_unlock(unsigned long flags) +static inline void gic_migration_unlock(void) { - raw_spin_unlock_irqrestore(&cpu_map_migration_lock, flags); + read_unlock(&cpu_map_migration_lock); } #else -static inline void gic_migration_lock(unsigned long *flags) {} -static inline void gic_migration_unlock(unsigned long flags) {} +static inline void gic_migration_lock(void) {} +static inline void gic_migration_unlock(void) {} #endif /* @@ -647,12 +650,20 @@ static void __init gic_pm_init(struct gic_chip_data *gic) #endif #ifdef CONFIG_SMP +/* + * Raise the specified IPI on all cpus set in mask. + * + * This function is safe to call from all calling contexts, including + * FIQ handlers. It relies on gic_migration_lock() being multiply acquirable + * to avoid deadlocks when the function is re-entered at different + * exception levels. + */ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { int cpu; - unsigned long flags, map = 0; + unsigned long map = 0; - gic_migration_lock(&flags); + gic_migration_lock(); /* Convert our logical CPU mask into a physical one. */ for_each_cpu(cpu, mask) @@ -667,7 +678,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) /* this always happens on GIC0 */ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); - gic_migration_unlock(flags); + gic_migration_unlock(); } #endif @@ -715,7 +726,8 @@ int gic_get_cpu_id(unsigned int cpu) * Migrate all peripheral interrupts with a target matching the current CPU * to the interface corresponding to @new_cpu_id. The CPU interface mapping * is also updated. Targets to other CPU interfaces are unchanged. - * This must be called with IRQs locally disabled. + * This must be called from a task context and with IRQ and FIQ locally + * disabled. */ void gic_migrate_target(unsigned int new_cpu_id) { @@ -746,9 +758,9 @@ void gic_migrate_target(unsigned int new_cpu_id) * pending on the old cpu static. That means we can defer the * migration until after we have released the irq_controller_lock. */ - raw_spin_lock(&cpu_map_migration_lock); + write_lock(&cpu_map_migration_lock); gic_cpu_map[cpu] = 1 << new_cpu_id; - raw_spin_unlock(&cpu_map_migration_lock); + write_unlock(&cpu_map_migration_lock); /* * Find all the peripheral interrupts targetting the current