| Message ID | 1428699386-2622-1-git-send-email-dinguyen@opensource.altera.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi! dinguyen@opensource.altera.com writes: > From: Dinh Nguyen <dinguyen@opensource.altera.com> > > The CIU(Card Interface Unit) clock is used by the dw_mmc IP to clock an SD > card. The ciu_clk is the sdmmc_clk passed through a fixed divider of 4. This patch > adds the ciu_clk node and makes the sdmmc_clk it's parent. > > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> > --- > arch/arm/boot/dts/socfpga.dtsi | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > index d9176e6..25418ee 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/socfpga.dtsi > @@ -451,6 +451,14 @@ > clk-phase = <0 135>; > }; > > + ciu_clk: ciu_clk { > + #clock-cells = <0>; > + compatible = "altr,socfpga-gate-clk"; > + clocks = <&sdmmc_clk>; > + clk-gate = <0xa0 8>; > + fixed-divider = <4>; > + }; > + Hm, is this correct? The clk-gate at 0xa0 is for the SDMMC_CLK, no? Also, maybe the clock should be named "sdmmc_clk_divided" like in the datasheet, so it is easier to find. > nand_x_clk: nand_x_clk { > #clock-cells = <0>; > compatible = "altr,socfpga-gate-clk"; > @@ -635,7 +643,7 @@ > fifo-depth = <0x400>; > #address-cells = <1>; > #size-cells = <0>; > - clocks = <&l4_mp_clk>, <&sdmmc_clk>; > + clocks = <&l4_mp_clk>, <&ciu_clk>; > clock-names = "biu", "ciu"; > }; > Regards, Steffen
Hi Steffen, On 04/13/2015 03:10 AM, Steffen Trumtrar wrote: > > Hi! > > dinguyen@opensource.altera.com writes: >> From: Dinh Nguyen <dinguyen@opensource.altera.com> >> >> The CIU(Card Interface Unit) clock is used by the dw_mmc IP to clock an SD >> card. The ciu_clk is the sdmmc_clk passed through a fixed divider of 4. This patch >> adds the ciu_clk node and makes the sdmmc_clk it's parent. >> >> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> >> --- >> arch/arm/boot/dts/socfpga.dtsi | 10 +++++++++- >> 1 file changed, 9 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi >> index d9176e6..25418ee 100644 >> --- a/arch/arm/boot/dts/socfpga.dtsi >> +++ b/arch/arm/boot/dts/socfpga.dtsi >> @@ -451,6 +451,14 @@ >> clk-phase = <0 135>; >> }; >> >> + ciu_clk: ciu_clk { >> + #clock-cells = <0>; >> + compatible = "altr,socfpga-gate-clk"; >> + clocks = <&sdmmc_clk>; >> + clk-gate = <0xa0 8>; >> + fixed-divider = <4>; >> + }; >> + > > Hm, is this correct? The clk-gate at 0xa0 is for the SDMMC_CLK, no? > Also, maybe the clock should be named "sdmmc_clk_divided" like in the > datasheet, so it is easier to find. > Well, I didn't want to go down the path of defining a new clock that is just a fork of the sdmmc_clk, so I just defined it as a gate-clock. I think ultimately the gating of the sdmmc_clk is being done. I can rename it to sdmmc_clk_divided. Dinh
Hi, On Fri, Apr 10, 2015 at 1:56 PM, <dinguyen@opensource.altera.com> wrote: > From: Dinh Nguyen <dinguyen@opensource.altera.com> > > The CIU(Card Interface Unit) clock is used by the dw_mmc IP to clock an SD > card. The ciu_clk is the sdmmc_clk passed through a fixed divider of 4. This patch > adds the ciu_clk node and makes the sdmmc_clk it's parent. > > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> > --- > arch/arm/boot/dts/socfpga.dtsi | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > index d9176e6..25418ee 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/socfpga.dtsi > @@ -451,6 +451,14 @@ > clk-phase = <0 135>; > }; > > + ciu_clk: ciu_clk { Can't say I'm an expert on socfpga, but seems like this clock is only for sdmmc, right? ...so its name ought to have sdmmc in its name? -Doug
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index d9176e6..25418ee 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -451,6 +451,14 @@ clk-phase = <0 135>; }; + ciu_clk: ciu_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&sdmmc_clk>; + clk-gate = <0xa0 8>; + fixed-divider = <4>; + }; + nand_x_clk: nand_x_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; @@ -635,7 +643,7 @@ fifo-depth = <0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clocks = <&l4_mp_clk>, <&ciu_clk>; clock-names = "biu", "ciu"; };