From patchwork Wed Apr 15 06:04:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Wang X-Patchwork-Id: 6218841 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AE08B9F2EC for ; Wed, 15 Apr 2015 06:07:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C4CAB20375 for ; Wed, 15 Apr 2015 06:07:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6CA42035E for ; Wed, 15 Apr 2015 06:07:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YiGRn-0001UJ-6L; Wed, 15 Apr 2015 06:05:15 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YiGRV-0000Rc-Ub for linux-arm-kernel@lists.infradead.org; Wed, 15 Apr 2015 06:04:59 +0000 Received: from 172.24.2.119 (EHLO szxeml428-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CMD23207; Wed, 15 Apr 2015 14:04:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.158.1; Wed, 15 Apr 2015 14:03:52 +0800 From: Zhou Wang To: Bjorn Helgaas , Mohit Kumar , Jingoo Han , Arnd Bergmann , Liviu Dudau Subject: [RFC PATCH 1/3] PCI: host: designware: support ARM64 Date: Wed, 15 Apr 2015 14:04:01 +0800 Message-ID: <1429077843-184462-2-git-send-email-wangzhou1@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1429077843-184462-1-git-send-email-wangzhou1@hisilicon.com> References: <1429077843-184462-1-git-send-email-wangzhou1@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150414_230458_429653_7964304E X-CRM114-Status: GOOD ( 10.84 ) X-Spam-Score: -0.0 (/) Cc: zhudacai@hisilicon.com, devicetree@vger.kernel.org, gabriele.paoloni@huawei.com, wangzhou.bry@gmail.com, linux-pci@vger.kernel.org, yuanzhichang@hisilicon.com, Zhou Wang , xiehaitao@huawei.com, zhangjukuo@huawei.com, liguozhu@hisilicon.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Zhou Wang --- drivers/pci/host/pcie-designware.c | 44 +++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 17ca986..e88a7d9 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "pcie-designware.h" @@ -31,6 +32,7 @@ #define PORT_LINK_MODE_1_LANES (0x1 << 16) #define PORT_LINK_MODE_2_LANES (0x3 << 16) #define PORT_LINK_MODE_4_LANES (0x7 << 16) +#define PORT_LINK_MODE_8_LANES (0xf << 16) #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) @@ -38,6 +40,7 @@ #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) +#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) #define PCIE_MSI_ADDR_LO 0x820 #define PCIE_MSI_ADDR_HI 0x824 @@ -68,14 +71,19 @@ #define PCIE_ATU_UPPER_TARGET 0x91C static struct hw_pci dw_pci; +static struct pci_ops dw_pcie_ops; static unsigned long global_io_offset; -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) +static inline struct pcie_port *sys_to_pcie(void *sys) { - BUG_ON(!sys->private_data); +#ifdef CONFIG_ARM + pci_sys_data *sys_data = (struct pci_sys_data *)sys; - return sys->private_data; + BUG_ON(!sys->private_data); + return sys_data->private_data; +#endif + return (struct pcie_port *)sys; } int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) @@ -502,6 +510,27 @@ int __init dw_pcie_host_init(struct pcie_port *pp) val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); +#ifdef CONFIG_ARM64 + struct pci_bus *bus; + LIST_HEAD(res); + + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); + if (ret) + return ret; + + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, + pp, &res); + if (!bus) + return -ENOMEM; + + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); + + pci_scan_child_bus(bus); + pci_assign_unassigned_bus_resources(bus); + pci_bus_add_devices(bus); +#endif + +#ifdef CONFIG_ARM #ifdef CONFIG_PCI_MSI dw_pcie_msi_chip.dev = pp->dev; dw_pci.msi_ctrl = &dw_pcie_msi_chip; @@ -514,6 +543,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) #ifdef CONFIG_PCI_DOMAINS dw_pci.domain++; #endif +#endif return 0; } @@ -704,6 +734,7 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; +#ifdef CONFIG_ARM static int dw_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; @@ -761,6 +792,7 @@ static struct hw_pci dw_pci = { .scan = dw_pcie_scan_bus, .map_irq = dw_pcie_map_irq, }; +#endif void dw_pcie_setup_rc(struct pcie_port *pp) { @@ -781,6 +813,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp) case 4: val |= PORT_LINK_MODE_4_LANES; break; + case 8: + val |= PORT_LINK_MODE_8_LANES; + break; } dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); @@ -797,6 +832,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp) case 4: val |= PORT_LOGIC_LINK_WIDTH_4_LANES; break; + case 8: + val |= PORT_LOGIC_LINK_WIDTH_8_LANES; + break; } dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);