From patchwork Mon Apr 27 21:38:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joachim Eastwood X-Patchwork-Id: 6283201 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E93E89F1C2 for ; Mon, 27 Apr 2015 21:42:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B127020306 for ; Mon, 27 Apr 2015 21:42:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C99E20340 for ; Mon, 27 Apr 2015 21:42:08 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ymqkh-0007BD-H1; Mon, 27 Apr 2015 21:39:43 +0000 Received: from mail-lb0-x22f.google.com ([2a00:1450:4010:c04::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ymqk1-0006xu-7t for linux-arm-kernel@lists.infradead.org; Mon, 27 Apr 2015 21:39:03 +0000 Received: by lbbqq2 with SMTP id qq2so92701367lbb.3 for ; Mon, 27 Apr 2015 14:38:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ac3Xkd9d9e36rn1kGOplANvhwDy2jWnWeEcCg9DL7zQ=; b=UdMHht56v/reuoJqe37gfW73wRibjiVXzG2mwGeFjkK4Bt22BP0mwf+xjddU6n9d+p VU0qf3x+vmNqaK9MBZdEuBZEBesSO9liluwLb+USOHy5a7NNnYtPOvrmGPDVGO54aw4W JjtojtAd8PZf88Q+0pQcCCAdRX+EO77l47Dc3tGZTzOfebFXipfU6glV6bSdmp34M1Az DSocrg8i2qOolImes9szTOC88zTMuPr1bnaYAcHJVzA+/NnPF9yTRmG6qdhXGj4Rt0au 1v3IuLBc+UDLIf6xZSfRJm0Qdpu7YCvE2VyKcPNOIQ1/hUpE/gxDb1hOtPT90n0FIyjW 573A== X-Received: by 10.152.5.7 with SMTP id o7mr11707252lao.51.1430170719908; Mon, 27 Apr 2015 14:38:39 -0700 (PDT) Received: from localhost.localdomain ([90.149.48.183]) by mx.google.com with ESMTPSA id o7sm5061382lbp.37.2015.04.27.14.38.38 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 27 Apr 2015 14:38:39 -0700 (PDT) From: Joachim Eastwood To: mturquette@linaro.org, sboyd@codeaurora.org, arnd@arndb.de, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/4] doc: dt: add documentation for lpc1850-ccu clk driver Date: Mon, 27 Apr 2015 23:38:13 +0200 Message-Id: <1430170693-28303-5-git-send-email-manabian@gmail.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1430170693-28303-1-git-send-email-manabian@gmail.com> References: <1430170693-28303-1-git-send-email-manabian@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150427_143901_516339_D008F937 X-CRM114-Status: GOOD ( 13.26 ) X-Spam-Score: -0.8 (/) Cc: devicetree@vger.kernel.org, Joachim Eastwood , ezequiel@vanguardiasur.com.ar, ariel.dalessandro@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT binding documentation for lpc1850-ccu clk driver. Signed-off-by: Joachim Eastwood --- .../devicetree/bindings/clock/lpc1850-ccu.txt | 146 +++++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-ccu.txt diff --git a/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt new file mode 100644 index 000000000000..1b45bc9f004f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt @@ -0,0 +1,146 @@ +* NXP LPC1850 Clock Control Unit (CCU) + +Each CGU base clock has several clock branches which can be turned on +or off independently by the Clock Control Units CCU1 or CCU2. The +branch clocks are distributed between CCU1 and CCU2. + + - Above text taken from NXP LPC1850 User Manual. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be "nxp,lpc1850-ccu" +- reg: + Shall define the base and range of the address space + containing clock control registers +- #clock-cells: + Shall have value <1>. The permitted clock-specifier values + are the branch clock names defined in table below. +- clocks: + Shall contain a list of phandles for the base clocks routed + from the CGU to the specific CCU. See mapping of base clocks + and CCU in table below. + +Which brach clocks that are available on the CCU depends on the +specific LPC part. + +CCU1 branch clocks: +Base clock Branch clock Description +BASE_APB3_CLK CLK_APB3_BUS APB3 bus clock. + CLK_APB3_I2C1 Clock to the I2C1 register interface + and I2C1 peripheral clock. + CLK_APB3_DAC Clock to the DAC register interface. + CLK_APB3_ADC0 Clock to the ADC0 register interface + and ADC0 peripheral clock. + CLK_APB3_ADC1 Clock to the ADC1 register interface + and ADC1 peripheral clock. + CLK_APB3_CAN0 Clock to the C_CAN0 register interface + and C_CAN0 peripheral clock. +BASE_APB1_CLK CLK_APB1_BUS APB1 bus clock. + CLK_APB1_MOTOCON_PWM Clock to the PWM Motor control block and + PWM Motor control peripheral clock. + CLK_APB1_I2C0 Clock to the I2C0 register interface and + I2C0 peripheral clock. + CLK_APB1_I2S Clock to the I2S0 and I2S1 register interfaces + and I2S0 and I2S1 peripheral clock. + CLK_APB1_CAN1 Clock to the C_CAN1 register interface and + C_CAN1 peripheral clock. +BASE_SPIFI_CLK CLK_SPIFI Clock for the SPIFI SCKI clock input. +BASE_CPU_CLK CLK_CPU_BUS M4 bus clock. + CLK_CPU_SPIFI Clock to the SPIFI register interface. + CLK_CPU_GPIO Clock to the GPIO register interface + CLK_CPU_LCD Clock to the LCD register interface. + CLK_CPU_ETHERNET Clock to the Ethernet register interface. + CLK_CPU_USB0 Clock to the USB0 register interface. + CLK_CPU_EMC Clock to the External memory controller. + CLK_CPU_SDIO Clock to the SD/MMC register interface. + CLK_CPU_DMA Clock to the DMA register interface. + CLK_CPU_CORE Clock to the Cortex-M core + CLK_CPU_SCT Clock to the SCT register interface. + CLK_CPU_USB1 Clock to the USB1 register interface. + CLK_CPU_EMC_DIV Clock to the EMC with clock divider. + CLK_CPU_FLASHA Clock to the flash bank A. + CLK_CPU_FLASHB Clock to the flash bank B. + CLK_CPU_M0APP Clock to the M0APP coprocessor. + CLK_CPU_ADCHS Clock to the ADCHS. + CLK_CPU_EEPROM Clock to the EEPROM. + CLK_CPU_WWDT Clock to the WWDT register interface. + CLK_CPU_UART0 Clock to the USART0 register interface. + CLK_CPU_UART1 Clock to the UART1 register interface. + CLK_CPU_SSP0 Clock to the SSP0 register interface. + CLK_CPU_TIMER0 Clock to the timer0 register interface and + timer0 peripheral clock. + CLK_CPU_TIMER1 Clock to the timer1 register interface and + timer1 peripheral clock. + CLK_CPU_SCU Clock to the System control unit register interface. + CLK_CPU_CREG Clock to the CREG register interface. + CLK_CPU_RITIMER Clock to the RI timer register interface and + RI timer peripheral clock. + CLK_CPU_UART2 Clock to the UART2 register interface. + CLK_CPU_UART3 Clock to the UART3 register interface. + CLK_CPU_TIMER2 Clock to the timer2 register interface and + timer2 peripheral clock. + CLK_CPU_TIMER3 Clock to the timer3 register interface and + timer3 peripheral clock. + CLK_CPU_SSP1 Clock to the SSP1 register interface. + CLK_CPU_QEI Clock to the QEI register interface and + QEI peripheral clock. +BASE_PERIPH_CLK CLK_PERIPH_BUS Clock to the peripheral bus and the + Cortex-M0 subsystem AHB multilayer matrix. + CLK_PERIPH_CORE Clock to the Cortex-M0 subsystem core. + CLK_PERIPH_SGPIO Clock to the SGPIO interface. +BASE_USB0_CLK CLK_USB0 USB0 peripheral clock. +BASE_USB1_CLK CLK_USB1 USB1 peripheral clock. +BASE_SPI_CLK CLK_SPI Clock to the SPI interface. +BASE_ADCHS_CLK CLK_ADCHS ADCHS clock. + +CCU2 branch clocks: +BASE_AUDIO_CLK CLK_AUDIO Audio system (I2S) clock. +BASE_UART3_CLK CLK_APB2_UART3 USART3 peripheral clock. +BASE_UART2_CLK CLK_APB2_UART2 USART2 peripheral clock. +BASE_UART1_CLK CLK_APB0_UART1 UART1 peripheral clock. +BASE_UART0_CLK CLK_APB0_UART0 USART0 peripheral clock. +BASE_SSP1_CLK CLK_APB2_SSP1 SSP1 peripheral clock. +BASE_SSP0_CLK CLK_APB0_SSP0 SSP0 peripheral clock. +BASE_SDIO_CLK CLK_SDIO SD/MMC peripheral clock. + +Not all branch clocks are available on all LPC parts. Check the user +manual for your specific part. + +Note that CLK_M3_x and CLK_M4_x have been renamed to CLK_CPU_x here +be more generic since both LPC18xx (M3) and LPC43xx (M4) are +supported. + + +Example board file: + +soc { + ccu1: ccu@40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + }; + + ccu2: ccu@40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + }; + + /* A user of CCU brach clocks */ + uart1: serial@40082000 { + ... + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + ... + }; +};