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client-ip=66.35.236.227; helo=sj-itexedge03.altera.priv.altera.com; Received: from sj-itexedge03.altera.priv.altera.com (66.35.236.227) by BN1AFFO11OLC002.mail.protection.outlook.com (10.58.53.73) with Microsoft SMTP Server (TLS) id 15.1.160.8 via Frontend Transport; Tue, 28 Apr 2015 15:15:52 +0000 Received: from na01-bl2-obe.outbound.protection.outlook.com (207.46.163.206) by webmail.altera.com (66.35.236.227) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 28 Apr 2015 08:14:12 -0700 Authentication-Results: codeaurora.org; dkim=none (message not signed) header.d=none; Received: from linux-builds1.altera.com (64.129.157.38) by BN3PR03MB1368.namprd03.prod.outlook.com (25.163.34.154) with Microsoft SMTP Server (TLS) id 15.1.148.16; Tue, 28 Apr 2015 15:15:32 +0000 From: To: , Subject: [PATCHv2 1/4] clk: socfpga: update clk.h so for Arria10 platform to use Date: Tue, 28 Apr 2015 10:10:13 -0500 Message-ID: <1430233816-32635-2-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 In-Reply-To: <1430233816-32635-1-git-send-email-dinguyen@opensource.altera.com> References: <1430233816-32635-1-git-send-email-dinguyen@opensource.altera.com> MIME-Version: 1.0 X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BY2PR06CA049.namprd06.prod.outlook.com (10.141.250.167) To BN3PR03MB1368.namprd03.prod.outlook.com (25.163.34.154) X-Microsoft-Antispam: UriScan:; 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X-Spam-Score: -0.2 (/) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, dinh.linux@gmail.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, Dinh Nguyen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 4 ---- drivers/clk/socfpga/clk.h | 6 +++++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index dd3a78c..607ab35 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -32,14 +32,10 @@ #define SOCFPGA_MMC_CLK "sdmmc_clk" #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 -#define streq(a, b) (strcmp((a), (b)) == 0) - #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) /* SDMMC Group for System Manager defines */ #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) { diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d291f60..b09a5d5 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -26,9 +26,13 @@ #define CLKMGR_L4SRC 0x70 #define CLKMGR_PERPLL_SRC 0xAC -#define SOCFPGA_MAX_PARENTS 3 +#define SOCFPGA_MAX_PARENTS 5 #define div_mask(width) ((1 << (width)) - 1) +#define streq(a, b) (strcmp((a), (b)) == 0) +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) + extern void __iomem *clk_mgr_base_addr; void __init socfpga_pll_init(struct device_node *node);