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[213.39.132.233]) by mx.google.com with ESMTPSA id e2sm3400832wij.5.2015.04.30.10.46.05 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Apr 2015 10:46:06 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Subject: [PATCH 4/4] clk: si5351: Reset PLL after rate change Date: Thu, 30 Apr 2015 19:45:54 +0200 Message-Id: <1430415954-29517-5-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1430415954-29517-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1430415954-29517-1-git-send-email-sebastian.hesselbarth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150430_104627_795087_964A6D2E X-CRM114-Status: GOOD ( 11.85 ) X-Spam-Score: -0.8 (/) Cc: devicetree@vger.kernel.org, Mike Turquette , Jean-Francois Moine , Stephen Boyd , linux-kernel@vger.kernel.org, Michael Welling , Russell King , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When changing PLL rate significantly, PLLs have to be reset. Add a function to perform and check for successful PLL reset. Signed-off-by: Sebastian Hesselbarth --- Cc: Mike Turquette Cc: Stephen Boyd Cc: Jean-Francois Moine Cc: Michael Welling Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/clk-si5351.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index beeb57bbb04c..9b97c134e3c1 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -366,6 +366,32 @@ static const struct clk_ops si5351_vxco_ops = { * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3) * */ +static int si5351_pll_reset(struct si5351_hw_data *hwdata) +{ + unsigned long timeout; + u8 mask = (hwdata->num == 0) ? + SI5351_STATUS_LOL_A : SI5351_STATUS_LOL_B; + + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + (hwdata->num == 0) ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); + timeout = jiffies + msecs_to_jiffies(100); + do { + if ((si5351_reg_read(hwdata->drvdata, SI5351_DEVICE_STATUS) & + mask) == 0) + break; + if (time_after(jiffies, timeout)) { + dev_err(&hwdata->drvdata->client->dev, + "timeout waiting for pll %d reset\n", + hwdata->num); + return -EBUSY; + }; + udelay(250); + } while (true); + + return 0; +} + static int _si5351_pll_reparent(struct si5351_driver_data *drvdata, int num, enum si5351_pll_src parent) { @@ -519,6 +545,9 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, SI5351_CLK_INTEGER_MODE, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); + /* reset pll after rate change */ + si5351_pll_reset(hwdata); + dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", __func__, __clk_get_name(hwdata->hw.clk),