From patchwork Fri May 1 04:41:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 6308191 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 698919F32E for ; Fri, 1 May 2015 04:44:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 71FAB20256 for ; Fri, 1 May 2015 04:44:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D90520211 for ; Fri, 1 May 2015 04:44:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yo2lv-0001y4-O0; Fri, 01 May 2015 04:41:55 +0000 Received: from mail-ob0-x22d.google.com ([2607:f8b0:4003:c01::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yo2lq-0001r8-3N for linux-arm-kernel@lists.infradead.org; Fri, 01 May 2015 04:41:51 +0000 Received: by obfe9 with SMTP id e9so59574968obf.1 for ; Thu, 30 Apr 2015 21:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=wMapQbs05KkVTVv0HvvUWqaZEkO3qGrF+W/fNgInJxk=; b=OlHzIXEmJWafwwkUbZih+uX3NlmvtFcQsUnm2aviEBAhY1X7rH8hG5CywTrM4PbVhr htKVedaeovWg6UQFB91Dof3eZpTtX7NMtZ0Lq8PX6EL3Jv4+7iSBl3PM09/WO42XDCZK uPMbJ1wwXKC5oDZJ7kt0p/Z0cvRjUmtnp7I76VF4NGrsvORUbQ7K9sF/aY6tlHvXCTbD 3FnCeBRl19bFJ7vzuz25Ra0wzDArYjSfwVX6OI+A5o3paaCDSslDK8xFrmkWEmp931rc 7RpBrl8VLmzl5VeCa8eXUs5AYDqQq5XeYwZMN+tfyKhtr0snIfxEa2ssAhTgFTgArz0T mPdg== X-Received: by 10.202.87.200 with SMTP id l191mr5945703oib.83.1430455288507; Thu, 30 Apr 2015 21:41:28 -0700 (PDT) Received: from rob-hp-laptop.herring.priv (72-48-98-129.dyn.grandenetworks.net. [72.48.98.129]) by mx.google.com with ESMTPSA id a76sm2524284oig.11.2015.04.30.21.41.27 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 21:41:28 -0700 (PDT) From: Rob Herring To: Mike Turquette , Stephen Boyd Subject: [PATCH 1/2] dt-bindings: Add pxa1928 clock binding Date: Thu, 30 Apr 2015 23:41:10 -0500 Message-Id: <1430455271-20195-1-git-send-email-robh@kernel.org> X-Mailer: git-send-email 2.1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150430_214150_271002_1E25E435 X-CRM114-Status: UNSURE ( 9.99 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Rob Herring , Ian Campbell , linux-kernel@vger.kernel.org, Kumar Gala , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the clock binding documentation for the Marvell PXA1928 SOC. The PXA1928 has 3 clock control blocks for different subsystems of the chip. Signed-off-by: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala --- .../devicetree/bindings/clock/marvell,pxa1928.txt | 21 ++++++++ include/dt-bindings/clock/marvell,pxa1928.h | 57 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1928.txt create mode 100644 include/dt-bindings/clock/marvell,pxa1928.h diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt b/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt new file mode 100644 index 0000000..809c5a2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt @@ -0,0 +1,21 @@ +* Marvell PXA1928 Clock Controllers + +The PXA1928 clock subsystem generates and supplies clock to various +controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller +blocks called APMU, MPMU, and APBC roughly corresponding to internal buses. + +Required Properties: + +- compatible: should be one of the following. + - "marvell,pxa1928-apmu" - APMU controller compatible + - "marvell,pxa1928-mpmu" - MPMU controller compatible + - "marvell,pxa1928-apbc" - APBC controller compatible +- reg: physical base address of the clock controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Each clock is assigned an identifier and client nodes use the clock controller +phandle and this identifier to specify the clock which they consume. + +All these identifiers can be found in . diff --git a/include/dt-bindings/clock/marvell,pxa1928.h b/include/dt-bindings/clock/marvell,pxa1928.h new file mode 100644 index 0000000..c393ca2 --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1928.h @@ -0,0 +1,57 @@ +#ifndef __DTS_MARVELL_PXA1928_CLOCK_H +#define __DTS_MARVELL_PXA1928_CLOCK_H + +/* + * Clock ID values here correspond to the control register offset/4. + */ + +/* apb periphrals */ +#define PXA1928_CLK_RTC 0 +#define PXA1928_CLK_TWSI0 1 +#define PXA1928_CLK_TWSI1 2 +#define PXA1928_CLK_TWSI2 3 +#define PXA1928_CLK_TWSI3 4 +#define PXA1928_CLK_OWIRE 5 +#define PXA1928_CLK_KPC 6 +#define PXA1928_CLK_TB_ROTARY 7 +#define PXA1928_CLK_SW_JTAG 8 +#define PXA1928_CLK_TIMER1 9 +#define PXA1928_CLK_UART0 0xb +#define PXA1928_CLK_UART1 0xc +#define PXA1928_CLK_UART2 0xd +#define PXA1928_CLK_GPIO 0xe +#define PXA1928_CLK_PWM0 0xf +#define PXA1928_CLK_PWM1 0x10 +#define PXA1928_CLK_PWM2 0x11 +#define PXA1928_CLK_PWM3 0x12 +#define PXA1928_CLK_SSP0 0x13 +#define PXA1928_CLK_SSP1 0x14 +#define PXA1928_CLK_SSP2 0x15 + +#define PXA1928_CLK_TWSI4 0x1f +#define PXA1928_CLK_TWSI5 0x20 +#define PXA1928_CLK_UART3 0x22 +#define PXA1928_CLK_THSENS_GLOB 0x24 +#define PXA1928_CLK_THSENS_CPU 0x26 +#define PXA1928_CLK_THSENS_VPU 0x27 +#define PXA1928_CLK_THSENS_GC 0x28 +#define PXA1928_APBC_NR_CLKS 0x30 + + +/* axi periphrals */ +#define PXA1928_CLK_SDH0 0x15 +#define PXA1928_CLK_SDH1 0x16 +#define PXA1928_CLK_USB 0x17 +#define PXA1928_CLK_NAND 0x18 +#define PXA1928_CLK_DMA 0x19 + +#define PXA1928_CLK_SDH2 0x3a +#define PXA1928_CLK_SDH3 0x3b +#define PXA1928_CLK_HSIC 0x3e +#define PXA1928_CLK_SDH4 0x57 +#define PXA1928_CLK_GC3D 0x5d +#define PXA1928_CLK_GC2D 0x5f + +#define PXA1928_APMU_NR_CLKS 0x60 + +#endif